ST7263BK6 STMicroelectronics, ST7263BK6 Datasheet - Page 29
ST7263BK6
Manufacturer Part Number
ST7263BK6
Description
LOW SPEED USB 8-BIT MCU FAMILY WITH UP TO 32K FLASH/ROM, DFU CAPABILITY, 8-BIT ADC, WDG, TIMER, SCI and I2C
Manufacturer
STMicroelectronics
Datasheet
1.ST7263BH6.pdf
(186 pages)
Specifications of ST7263BK6
4, 8, 16 Or 32 Kbytes Program Memory
high density Flash (HDFlash), FastROM or ROM with Read-Out and Write protection
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- Download datasheet (3Mb)
ST7263Bxx
Condition Code register (CC)
Reset value: 111x1xxx
The 8-bit Condition Code register contains the interrupt mask and four flags representative
of the result of the instruction just executed. This register can also be handled by the PUSH
and POP instructions.
These bits can be individually tested and/or controlled by specific instructions.
7
1
Bit 4 H Half carry
Bit 3 I Interrupt mask
6
1
This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU
during an ADD or ADC instruction. It is reset by hardware during the same
instructions.
0: No half carry has occurred.
1: A half carry has occurred.
This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD
arithmetic subroutines.
This bit is set by hardware when entering in interrupt or by software to disable all
interrupts except the TRAP software interrupt. This bit is cleared by software.
0: Interrupts are enabled.
1: Interrupts are disabled.
This bit is controlled by the RIM, SIM and IRET instructions and is tested by the
JRM and JRNM instructions.
Note: Interrupts requested while I is set are latched and can be processed when I
is cleared. By default an interrupt routine is not interruptible because the I bit
is set by hardware at the start of the routine and reset by the IRET
instruction at the end of the routine. If the I bit is cleared by software in the
interrupt routine, pending interrupts are serviced regardless of the priority
level of the current interrupt routine.
5
1
Doc ID 7516 Rev 8
H
4
Read/write
3
I
N
2
Central processing unit
1
Z
C
0
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