71M6511 Maxim, 71M6511 Datasheet - Page 20

• Manufacturer Part Number: 71M6511
• Description: The 71M6511 and 71M6511H are highly integrated SoCs with an MPU core, RTC, flash, and LCD driver
• Manufacturer: Maxim

P0
DIR0
P1
DIR1
P2
DIR2
ERASE
PGADDR
EEDATA
EECTRL
Port Registers: The I/O ports are controlled by Special Function Registers P0, P1, and P2. The contents of the SFR can be
observed on corresponding pins on the chip. Writing a ‘1’ to any of the ports (see Table 11) causes the corresponding pin to
be at high level (V3P3), and writing a ‘0’ causes the corresponding pin to be held at low level (GND). The data direction
registers DIR0, DIR1, and DIR2 define individual pins as input or output pins (see section On-Chip Resources – DIO Ports for
details).
Register
All four ports on the chip are bi-directional. Each of them consists of a Latch (SFR ‘P0’ to ‘P3’), an output driver, and an input
buffer, therefore the MPU can output or read data through any of these ports. Even if a DIO pin is configured as an output, the
state of the pin can still be read by the MPU, for example when counting pulses issued via DIO pins that are under CE control.
Special Function Registers Specific to the 71M6511
Table 12 shows the location and description of the 71M6511-specific SFRs.
Register
Page: 20 of 98
A Maxim Integrated Products Brand
FLSH_ERASE
FLSH_PGADR
Addres
Alternative
0x80
0xA2
0x90
0x91
0xA0
0xA1
SFR
s
Name
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Addres
0xB7
0x9E
0x9F
0x94
SFR
Register for port 0 read and write operations (pins DIO4…DIO7)
Data direction register for port 0. Setting a bit to 1 means that the corresponding pin is
an output.
Register for port 1 read and write operations (pins DIO8…DIO15)
Data direction register for port 1.
Register for port 2 read and write operations (pins DIO16-DIO17)
Data direction register for port 2.
Description
s
© 2005–2010 Teridian Semiconductor Corporation
R/W
R/W
R/W
R/W
W
Table 11: Port Registers
This register is used to initiate either the Flash Mass Erase cycle or
the Flash Page Erase cycle. Specific patterns are expected for
FLSH_ERASE in order to initiate the appropriate Erase cycle (default =
0x00).
0x55 – Initiate Flash Page Erase cycle. Must be proceeded by a write
0xAA – Initiate Flash Mass Erase cycle. Must be proceeded by a
Any other pattern written to FLSH_ERASE will have no effect.
Flash Page Erase Address register containing the flash memory
page address (page 0 thru 127) that will be erased during the Page
Erase cycle (default = 0x00).
Must be re-written for each new Page Erase cycle.
I2C EEPROM interface data register
I2C EEPROM interface control register. If the MPU wishes to write a
byte of data to EEPROM, it places the data in EEDATA and then
writes the ‘Transmit’ code to EECTRL. The write to EECTRL initiates
the transmit sequence. See the section I2C Interface (EEPROM) for
a description of the command and status bits available for EECTRL.
Description
to FLSH_PGADR @ SFR 0xB7.
write to FLSH_MEEN @ SFR 0xB2 and the debug port must
be enabled.
Single-Phase Energy Meter IC
71M6511/71M6511H
DATA SHEET
NOVEMBER 2010
V2.7