71M6511 Maxim, 71M6511 Datasheet - Page 59

• Manufacturer Part Number: 71M6511
• Description: The 71M6511 and 71M6511H are highly integrated SoCs with an MPU core, RTC, flash, and LCD driver
• Manufacturer: Maxim

I/O RAM (Configuration RAM) – Alphabetical Order
Many functions of the chip can be controlled via the I/O RAM (Configuration RAM). The CE will also take some of its para-
meters from the I/O RAM.
Bits with a W (write) direction are written by the MPU into I/O RAM. Typically, they are initially stored in flash memory and
copied to the I/O RAM by the MPU. Some of the more frequently programmed bits are mapped to the MPU SFR memory
space. The remaining bits are mapped to 2xxx. Bits with R (read) direction can only be read by the MPU. On power up, all
bits are cleared to zero unless otherwise stated. Generic SFR registers are not listed.
Name
ADC_DIS
CE_EN
CHOP_EN[1:0]
RESERVED
CKOUT_DIS
RESERVED
RESERVED
DIO_R4[2:0]
DIO_R5[2:0]
DIO_R6[2:0]
DIO_R7[2:0]
DIO_R8[2:0]
DIO_R9[2:0]
DIO_R10[2:0]
DIO_R11[2:0]
DIO_DIR0[7:4]
Page: 59 of 98
A Maxim Integrated Products Brand
Location
[Bit(s)]
2005[3]
2000[4]
2002[5:4]
2004[5]
2004[4]
2003[4:3]
2003[2:0]
200B[2:0]
200B[6:4]
200C[2:0]
200C[6:4]
200D[2:0]
200D[6:4]
200E[2:0]
200E[6:4]
SFR A2
© 2005–2010 Teridian Semiconductor Corporation
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Dir
R
Description
Disables ADC and removes bias current
CE enable.
Chop enable for the reference band gap circuit.
00: enabled 01: disabled 10: disabled 11: enabled
Must be 0.
CKOUT Disable. When zero, CKTEST is an active output.
Must be 0.
Reserved
Connects dedicated I/O pins 4 to 11 to selectable internal resources. If
more than one input is connected to the same resource, the ‘Multiple’
column below specifies how they are combined. See Software User’s
Guide for details).
Programs the direction of DIO pins 7 through 4. 1 indicates output.
Ignored if the pin is not configured as I/O. See DIO_PV and DIO_PW
for special option for DIO6 and DIO7 outputs. See DIO_EEX for special
option for DIO4 and DIO5.
Note: Bit 0, Bit 1, Bit 2 and Bit 3 must be set to 1.
DIO_GP
0
1
2
3
4
5
6
7
High priority I/O interrupt (int0 falling)
Resource
NONE
Reserved
T0 (counter0 clock)
T1 (counter1 clock)
High priority I/O interrupt (int0 rising)
Low priority I/O interrupt (int1 rising)
Low priority I/O interrupt (int1 falling)
Single-Phase Energy Meter IC
71M6511/71M6511H
DATA SHEET
Multiple
NOVEMBER 2010
OR
OR
OR
OR
OR
OR
OR
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V2.7