71M6531D Maxim, 71M6531D Datasheet - Page 118
71M6531D
Manufacturer Part Number
71M6531D
Description
The 71M6531D/F and 71M6532D/F are highly integrated SoC devices with an MPU core, RTC, flash, and LCD driver
Manufacturer
Maxim
Datasheet
1.71M6531D.pdf
(120 pages)
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Data Sheet 71M6531D/F-71M6532D/F
Appendix B: Revision History
118
Revision
1.3
June 9, 2010
Date
© 2005-2010 TERIDIAN Semiconductor Corporation
1) Throughout document: Added bit ranges to all register fields where
2)
3)
4)
5)
6)
7)
8)
9)
11)
12)
13)
14)
15)
16)
17) Corrected values for EXT_PULSE in description of internal pulse
10)
missing (e.g. MPU_DIV[2:0]).
Figure
1.4 80515 MPU Core
1.5.2 Internal Clocks
(Page 36)
(Page 38) Added caution concerning frequency relationship to
1.5.3 Real-Time Clock (RTC):
observing RTC timing on TMUXOUT pin, corrected values for
RTCA_ADJ, and achievable frequency step.
1.5.9 Digital IO – Common Characteristics for 71M6531D/F and
71M6532D/F
Added caution about not sourcing current in or out of DIO pins.
Updated
1.5.13 Battery Monitor
ADC data.
1.5.15 SPI Slave Port
access via the SPI interface. Added
2.3 Battery Modes
cautions for switching between modes and factory programming of
the first 6 flash addresses.
Added SFR register addresses where needed.
(Page 19)
(Page 19) Changed providing Library to providing demonstration
(Page 20) Added note about MUX_DIV=0 disables ADC output.
(Page
(Page 22) Added P1-P3 to
(Page 23) Updated Data Pointer description.
(Page 24)
(Page 26)
(Page 27) Added caution on proper way to clear flag bits.
(Page 30)
(Page 31)
analog input pins requiring sensors with low source impedance.
3.15 MPU Firmware
source code provided.
3.16 Crystal Oscillator
rejecting electromagnetic interference.
Table 54: I/O RAM Map in Functional Order
Unused and NVRAM locations.
4.3.4 Environment:
parameter dependence on CE code environment.
4.3.6 CE Status and Control
Updated description of F0 in
Updated descriptions in
VBAT_SUM_X in
4.3.7 CE Transfer Variables:
specific CE code.
frequencies.
source code.
buffers.
3.1 Connection of Sensors
1,
21)
Figure
Figure 10 : Connecting an External Load to DIO Pins.
1.4.9
Table
Table
Table
See restrictions on INTBITS register.
Table
1.4.6
(Page 45):
2: corrected name for PSDI and PSDO signals.
Interrupts: Clarified External vs Internal interrupts.
Table 63
UARTs: Clarified SOBUF, S1BUF as Tx and Rx
25: Added Interrupt sources for Ext. Interrupts 2-6.
37: Changed frequencies to exact frequencies.
(page
6: Change approximate frequencies to exact
14: Updated description for FWCOL0, FWCOL1.
Added comment concerning importance of
(page 70): Modified to indicate demonstration
(page 49): Clarified description of I/O RAM
(Page 46): Corrected RAM address for
(page 70): Updated caution concerning
56,
Description
(page 93).
Table 58
Table
57): Added details on software pre-
(page 89):
(Page 39) Added description for
Updated description of
(page 63): Added note concerning
Table
10.
(page 91).
Table 50.
57.
(page 72): Updated
FDS 6531/6532 005
v1.3
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