71M6531D Maxim, 71M6531D Datasheet - Page 67
71M6531D
Manufacturer Part Number
71M6531D
Description
The 71M6531D/F and 71M6532D/F are highly integrated SoC devices with an MPU core, RTC, flash, and LCD driver
Manufacturer
Maxim
Datasheet
1.71M6531D.pdf
(120 pages)
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71M6531D-IM/F
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ceramic capacitor, as shown in
infrared diode and phototransistor implementing a FLAG interface).
for UART1. The OPT_TX pin becomes active when the I/O RAM register OPT_TXE is set to 00.
FDS 6531/6532 005
3.7
µWire EEPROMs and other compatible devices should be connected to the DIO pins DIO4 and DIO5, as
shown in
•
3.8
The UART0 RX pin should be pulled down by a 10 kΩ resistor and additionally protected by a 100 pF
3.9
The OPT_TX and OPT_RX pins can be used for a regular serial interface (by connecting a RS-232
transceiver for example), or they can be used to directly operate optical components (for example, an
v1.3
DIO5 connects to both the DI and DO pins of the three-wire device.
The CS pin must be connected to a vacant DIO pin of the 71M6531.
In order to prevent bus contention, a 10 kΩ to resistor is used to separate the DI and DO signals.
The CS and CLK pins should be pulled down with resistors to prevent operation of the three-wire device
on power-up, before the 71M6531 can establish a stable signal for CS and CLK.
The DIO_EEX[1:0] register in I/O RAM must be set to 2 (b10) in order to convert the DIO pins DIO4
and DIO5 to µWire pins.
Connecting Three-Wire EEPROMs
UART0 (TX/RX)
Optical Interface (UART1)
Figure 34
The µ-Wire EEPROM interface is only functional when MPU_DIV[2:0] = 000.
and described below:
© 2005-2010 TERIDIAN Semiconductor Corporation
71M6531D/F, 71M6532D/F
Figure 34: Three-Wire EEPROM Connection
Figure
71M653X
Figure 35: Connections for UART0
V3P3D
DIO4
DIO5
DIOn
35.
TX
RX
100 kΩ
100 pF
10 k Ω
100 kΩ
10 k Ω
Figure 36
Data Sheet 71M6531D/F-71M6532D/F
TX
RX
VCC
CLK
DO
CS
DI
EEPROM
shows the basic connections
67
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