71M6531D Maxim, 71M6531D Datasheet - Page 94
71M6531D
Manufacturer Part Number
71M6531D
Description
The 71M6531D/F and 71M6532D/F are highly integrated SoC devices with an MPU core, RTC, flash, and LCD driver
Manufacturer
Maxim
Datasheet
1.71M6531D.pdf
(120 pages)
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where F
register with the PULSE_FAST and PULSE_SLOW bits).
Data Sheet 71M6531D/F-71M6532D/F
The maximum time jitter is 67 µs and is independent of the number of pulses measured. Thus, if the pulse
generator is monitored for one second, the peak jitter is 67 ppm. After 10 seconds, the peak jitter is 6.7 ppm.
The average jitter is always zero. If it is attempted to drive either pulse generator faster than its maximum
rate, it will simply output at its maximum rate without exhibiting any rollover characteristics. The actual
pulse rate, using WSUM as an example, is:
4.3.9
Table 65
94
Address
Address
0x21
0x41
0x42
0x43
0x44
0x38
0x10
0x11
0x12
0x13
0x18
CE
CE
S
CE Calibration Parameters
lists the parameters that are typically entered to effect calibration of meter accuracy.
= sampling frequency (2520.6 Hz) and X = Pulse speed factor (as defined in the CECONFIG
APULSEW
APULSER
APULSE2
APULSE3
PHADJ_A
WRATE
WIDTH
CAL_VA
CAL_VB
PULSE
CAL_IA
CAL_IB
Name
Name
© 2005-2010 TERIDIAN Semiconductor Corporation
Default
Default
16384
16384
16384
16384
827
12
0
0
0
0
Table 64: CE Pulse Generation Parameters
0
Table 65: CE Calibration Parameters
RATE
Kh = VMAX*IMAX*47.1132 / (In_8*WRATE*N
default value results in a Kh of 1.0 Wh/pulse when 2520 samples
are taken in each accumulation interval (and VMAX=600,
IMAX = 442 [for 400µΩ shunt], In_8 = 1, X = 6).
Maximum value = 2
Watt pulse generator input (see DIO_PW bit). The output pulse
rate is: APULSEW * F
and can be loaded during a computation interval. The change will
take effect at the beginning of the next interval.
VAR pulse generator input (see DIO_PV bit). The output pulse rate
is: APULSER * F
can be loaded during a computation interval. The change will take
effect at the beginning of the next interval.
Third pulse generator input (see DIO_PV bit). The output pulse
rate is: APULSE2 * F
and can be loaded during a computation interval. The change will
take effect at the beginning of the next interval.
Fourth pulse generator input (see DIO_PV bit). The output pulse
rate is: APULSE3 * F
and can be loaded during a computation interval. The change will
take effect at the beginning of the next interval.
Register for pulse width control of XPULSE and YPULSE. The max-
imum pulse width is (2*PULSEWIDTH+1)*(1/FS). The default value
will generate pulses of 10 ms width at FS = 2520.62 Hz.
These constants control the gain of their respective channels. The
nominal value for each parameter is 2
channel is directly proportional to its gain constant. Thus, if the
gain of the IA channel is 1% slow, CAL_IA should be scaled by
1/(1 – 0.01) and the resulting value is 16549.
These two constants control the CT phase compensation. No
compensation occurs when PHADJ_X = 0. As PHADJ_X is increased,
more compensation (lag) is introduced. Range: ± 2
desired to delay the current by the angle Φ, the equations are:
=
WRATE
⋅
WSUM
S
2
*2
46
-32
15
S
S
S
*2
*2
* WRATE * X * 2
* 2
-1.
⋅
-32
-32
F
-32
S
* WRATE * X * 2
* WRATE * X * 2
⋅
* WRATE * X * 2
X
Description
Description
Hz
,
-14
14
. This input is buffered and
= 16384. The gain of each
-14
-14
-14
. This input is buffered
. This input is buffered
. This input is buffered
ACC
*X) Wh/pulse. The
FDS 6531/6532 005
15
– 1. If it is
v1.3
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