71M6543F Maxim, 71M6543F Datasheet - Page 140
71M6543F
Manufacturer Part Number
71M6543F
Description
The 71M6543F/71M6543H are Teridian's 4th-generation polyphase metering system-on-chips (SoCs) with a 5MHz, 8051-compatible MPU core, low-power real-time clock (RTC) with digital temperature compensation, flash memory, and LCD driver
Manufacturer
Maxim
Datasheet
1.71M6543F.pdf
(157 pages)
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71M6543F/H and 71M6543G/GH Data Sheet
6.4.9 2.5 V Voltage Regulator – Battery Power
6.4.10 Crystal Oscillator
6.4.11 Phase-Locked Loop (PLL)
PARAMETER
PLL Power-up Settling Time
PLL_FAST settling time
PLL SLP to MSN Settling Time
6.4.12 LCD Drivers
PARAMETER
VLCD Current
Note:
6.4.13 VLCD Generator
140
Parameter
V2P5
V2P5 load regulation
Voltage Overhead 2V − VBAT-VDD
Parameter
Maximum Output Power to Crystal
XIN to XOUT Capacitance
(see note 1)
Capacitance change on XOUT
Note:
1. These specifications apply to all COM and SEG pins.
1. LCD_VMODE=3, LCD_ON=1, LCD_BLANK=0, LCD_MODE=6, LCD_CLK=2.
2. Output load is 74 pF per SEG and COM pin.
1. Guaranteed by design; not production tested.
PLL_FAST rise
PLL_FAST fall
Table 99: Low-Power Voltage Regulator Performance Specifications
VLCD=3.3, all LCD map bits=0
VLCD=5.0, all LCD map bits=0
Table 100: Crystal Oscillator Performance Specifications
Table 102: LCD Drivers Performance Specifications
© 2008–2011 Teridian Semiconductor Corporation
Table 101: PLL Performance Specifications
Table 103: VLCD Generator Specifications
PLL_FAST =0,
V3P3 = 0 to 3.3 V step
Measured from first edge of MCK
(TMUX2OUT pin)
V3P3=0, VBAT=3.8 to 2.0 V
PLL_FAST =0
CONDITION
Condition
Crystal connected, see note 1
RTC_ADJ = 7F to 0,
Bias voltage = unbiased
Vpp = 0.1 V
Condition
VBAT = 3.0 V - 3.8 V,
V3P3 = 0 V, I
VBAT = 3.3 V, V3P3 = 0 V,
I
I
V3P3 = 0 V.
LOAD
LOAD
= 0 mA to 1 mA
= 0ma, VBAT = 2.0 V,
CONDITION
LOAD
= 0 mA
MIN
MIN
2.55
Min
Min
TYP MAX
TYP MAX
3
3
3
3
2.65
Typ
Typ
15
2
3
Max
Max
2.75
200
40
UNIT
1
3
uA
uA
UNIT
ms
ms
ms
ms
Unit
Unit
mV
mV
μW
pF
pF
V
v1.2
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