71M6543F Maxim, 71M6543F Datasheet - Page 50

• Manufacturer Part Number: 71M6543F
• Description: The 71M6543F/71M6543H are Teridian's 4th-generation polyphase metering system-on-chips (SoCs) with a 5MHz, 8051-compatible MPU core, low-power real-time clock (RTC) with digital temperature compensation, flash memory, and LCD driver
• Manufacturer: Maxim

The PLL is only turned off in SLP mode or in LCD mode when LCD_BSTE is disabled. The LCD_BSTE
value depends on the setting of the LCD_VMODE [1:0] field (see
When the part is waking up from SLP or LCD modes, the PLL is turned on in 6.29 MHz mode, and the
PLL frequency is not be accurate until the PLL_OK (SFR 0xF9[4]) flag rises. Due to potential overshoot, the
MPU should not change the value of PLL_FAST until PLL_OK is true.
71M6543F/H and 71M6543G/GH Data Sheet
Although the oscillator may appear to work when VBAT is not connected, this mode of operation is not re-
commended.
2.5.3 PLL and Internal Clocks
Timing for the device is derived from the 32.768 kHz crystal oscillator output that is multiplied by a PLL by
600 to obtain 19.660800 MHz, the master clock (MCK). All on-chip timing, except for the RTC clock, is
derived from MCK.
The two general-purpose counter/timers contained in the MPU are controlled by CKMPU (see
Timers and
The master clock can be boosted to 19.66 MHz by setting the PLL_FAST bit = 1 (I/O RAM 0x2200[4]) and
can be reduced to 6.29 MHz by PLL_FAST = 0. The MPU clock frequency CKMPU is determined by
another divider controlled by the I/O RAM control field MPU_DIV[2:0] (I/O RAM 0x2200[2:0]) and can be
set to MCK*2
circuit also generates the 9.83 MHz clock for use by the emulator.
50
If VBAT_RTC is connected to a drained battery or disconnected, a battery test that sets
TEMP_BAT may drain the supply connected to VBAT_RTC and cause the oscillator to stop. A
stopped oscillator may force the device to reset. Therefore, an unexpected reset during a battery
test should be interpreted as a battery failure.
Counters).
-(MPU_DIV+2)
Table 42
where MPU_DIV[2:0] may vary from 0 to 4. When the ICE_E pin is high, the
© 2008–2011 Teridian Semiconductor Corporation
provides a summary of the clock functions and their controls.
Table
52).
2.4.7
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