TDA9898HN/V3,551 NXP Semiconductors, TDA9898HN/V3,551 Datasheet - Page 61

• Manufacturer Part Number: TDA9898HN/V3,551
• Description: IC IF PROCESSOR HYBRID 48-HVQFN
• Manufacturer: NXP Semiconductors
• Type: Demodulatorr

Specifications of TDA9898HN/V3,551

• Applications: TV
• Mounting Type: Surface Mount
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935288218551

NXP Semiconductors
Table 53.
V
f
for L); IF input from 50
B/G is 10 % and for L is 3 %; video signal in accordance with “ITU-T J.63 line 17 and line 330” or “NTC-7 Composite”;
internal Nyquist slope switched on (W7[0] = 0); measurements taken in test circuit of
TDA9897_TDA9898_4
Product data sheet
Symbol
V
R
C
R
I
Group delay select; pin GDS; see
V
I
I
V
I
Address select; pin ADRSEL
V
R
R
I
V
I
I
SC
swoff
sink(I)
source(I)
2
2
sink(I)
source(I)
P
ref(RMS)
GDS
I
C-bus transceiver
ADRSEL
C-bus voltage select; pin BVS
BVS
O
dec
swoff(FREF)
i
ADRSEL
= 5 V; T
= 32.875 MHz; PC / SC = 13 dB; f
amb
Characteristics
= 25 C; see
Parameter
RMS reference voltage
output resistance
decoupling capacitance
switch-off resistance on
pin FREF
switch-off current
voltage on pin GDS
input sink current
input source current
input voltage
voltage on pin ADRSEL
(DC)
input resistance
resistance on pin ADRSEL
voltage on pin BVS (DC)
input sink current
input source current
[30]
via broadband transformer 1 : 1; video modulation: Vestigial SideBand (VSB); residual carrier for
Table 24
…continued
Figure 24
for input frequencies; B/G standard is used for the specification (f
AF
= 400 Hz); input level V
and
Conditions
see
of external reference
signal source; AC-coupled
to external reference
signal source
to switch off reference
signal input by external
resistor wired between
pin FREF and GND
R
R
pin open-circuit
pin connected to V
pin connected to GND
GDEQ on; W11[2] = 0;
pin connected to GND
GDEQ on; W11[2] = 1;
pin open-circuit
GDEQ off; W11[2] = 1;
pin connected to GND
GDEQ off; W11[2] = 0;
pin open-circuit
pin open-circuit
for address select
pin open-circuit
pin connected to V
pin connected to GND
swoff(FREF)
swoff(FREF)
MAD1; pin connected to
GND
MAD3; pin connected to
GND via R
MAD4; pin connected to
V
MAD2; pin connected to
V
Rev. 04 — 25 May 2009
P
P
Figure 34
Table 50
via R
ADRSEL
= 3.9 k
= 22 k
ADRSEL
i(IF)
P
P
= 10 mV (RMS) (sync level for B/G; peak white level
TDA9897; TDA9898
[3]
Multistandard hybrid IF processing
Min
15
-
22
3.9
-
-
-
-
-
0
0.58V
0
0.58V
-
0
0.20V
0.66V
0.96V
-
42.3
-
-
-
Figure
P
P
P
P
P
51; unless otherwise specified.
Typ
150
-
100
-
-
25
V
-
-
-
-
-
-
0.5V
-
-
-
-
31
47
0.52V
-
-
P
P
P
PC
© NXP B.V. 2009. All rights reserved.
= 38.375 MHz;
Max
500
4.7
-
27
100
-
-
1
72
0.46V
V
0.46V
V
-
0.04V
0.34V
0.80V
V
-
51.7
-
10
60
P
P
P
P
P
P
P
P
Unit
mV
k
pF
k
V
V
V
V
V
V
V
V
V
V
k
k
V
61 of 103
A
A
A
A
A
A