74HCT2G125DC,125 NXP Semiconductors, 74HCT2G125DC,125 Datasheet - Page 7

• Manufacturer Part Number: 74HCT2G125DC,125
• Description: IC BUFF DVR TRI-ST DL 8VSSOP
• Manufacturer: NXP Semiconductors
• Series: 74HCTr

Specifications of 74HCT2G125DC,125

• Package / Case: US8, 8-VSSOP
• Logic Type: Buffer/Line Driver, Non-Inverting
• Number Of Elements: 2
• Number Of Bits Per Element: 1
• Current - Output High, Low: 6mA, 6mA
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Logic Family: HCT
• Number Of Channels Per Chip: 2
• Polarity: Non-Inverting
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• High Level Output Current: - 6 mA
• Input Bias Current (max): 20 uA
• Low Level Output Current: 6 mA
• Minimum Operating Temperature: - 40 C
• Output Type: 3-State
• Propagation Delay Time: 15 ns (Typ) @ 4.5 V
• Number Of Lines (input / Output): 2 / 2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 74HCT2G125DC-G; 74HCT2G125DC-G; 935274707125

NXP Semiconductors
12. Waveforms
Table 9.
74HC_HCT2G125_4
Product data sheet
Type
74HC2G125
74HCT2G125
Fig 6.
Fig 7.
Measurement points are given in
Logic levels: V
Propagation delays data input (nA) to output (nY)
Measurement points are given in
Logic levels: V
Enable and disable times
Measurement points
OL
OL
and V
and V
HIGH-to-OFF
OFF-to-HIGH
LOW-to-OFF
OFF-to-LOW
Input
V
0.5V
1.3 V
OH
OH
nOE input
output
M
output
are typical output voltage levels that occur with the output load.
are typical output voltage levels that occur with the output load.
CC
output
input
nA
nY
GND
GND
V
V
V
Table
Table
OH
CC
OL
GND
V
V
V
I
OH
OL
V
I
9.
9.
V
M
enabled
Rev. 04 — 4 July 2008
outputs
t
PLZ
V
t
Output
V
0.5V
1.3 V
PHZ
t
M
THL
M
V
CC
M
t
PHL
V
X
74HC2G125; 74HCT2G125
V
Y
disabled
outputs
10 %
V M
V
M
t
TLH
V
V
V
t
PZL
X
OL
OL
t
90 %
PZH
t
001aad982
PLH
+ 0.3 V
+ 0.3 V
V
M
V
M
Dual buffer/line driver; 3-state
outputs
enabled
mna362
V
V
V
Y
OH
OH
© NXP B.V. 2008. All rights reserved.
0.3 V
0.3 V
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