74LVT16244BDGG,118 NXP Semiconductors, 74LVT16244BDGG,118 Datasheet - Page 9

• Manufacturer Part Number: 74LVT16244BDGG,118
• Description: IC BUFF DVR TRI-ST 16BIT 48TSSOP
• Manufacturer: NXP Semiconductors
• Series: 74LVTr

Specifications of 74LVT16244BDGG,118

• Logic Type: Buffer/Line Driver, Non-Inverting
• Package / Case: 48-TSSOP
• Number Of Elements: 4
• Number Of Bits Per Element: 4
• Current - Output High, Low: 32mA, 64mA
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Logic Family: LVT
• Number Of Channels Per Chip: 16
• Polarity: Non-Inverting
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• High Level Output Current: - 32 mA
• Input Bias Current (max): 6000 uA
• Low Level Output Current: 64 mA
• Minimum Operating Temperature: - 40 C
• Output Type: 3-State
• Propagation Delay Time: 1.8 ns (Typ) @ 3.3 V
• Logical Function: Buffer/Line Driver
• Number Of Elements: 4
• Number Of Channels: 16
• Number Of Inputs: 16
• Number Of Outputs: 16
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 2.7V
• Quiescent Current: 6mA
• Technology: BiCMOS
• Pin Count: 48
• Mounting: Surface Mount
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Number Of Lines (input / Output): 16 / 16
• Package Type: TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935202990118

NXP Semiconductors
11. Waveforms
Table 8.
74LVT_LVTH16244B_8
Product data sheet
Input
V
1.5 V
Fig 6.
Fig 7.
M
Measurements points are given in
V
Propagation delay input (nAn) to output (nYn)
Measurements points are given in
V
3-state output enable and disable times
OL
OL
Measurement points
and V
and V
OH
OH
are typical voltage output levels that occur with the output load.
are typical voltage output levels that occur with the output load.
nYn output
nYn output
nOE input
Output
V
1.5 V
M
nYn output
nAn input
3.0 V
GND
V OH
V OL
0 V
V
Table
Table
I
All information provided in this document is subject to legal disclaimers.
GND
V
V
OH
OL
V
8.
8.
I
V
Rev. 08 — 22 March 2010
t
M
PLH
t
t
PZL
PZH
74LVT16244B; 74LVTH16244B
V
M
V
V
V
M
M
M
V
V
X
OL
+ 0.3 V
V
M
t
t
V
PLZ
PHZ
M
t
PHL
mna171
V
X
V
3.3 V 16-bit buffer/driver; 3-state
Y
001aae464
V
V
Y
OH
− 0.3 V
© NXP B.V. 2010. All rights reserved.
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