74LV541D,112 NXP Semiconductors, 74LV541D,112 Datasheet
74LV541D,112
Specifications of 74LV541D,112
74LV541D
935088020112
Related parts for 74LV541D,112
74LV541D,112 Summary of contents
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Octal buffer/line driver; 3-state Rev. 03 — 14 April 2009 1. General description The 74LV541 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC541 and 74HCT541. The 74LV541 has octal non-inverting buffer/line drivers with ...
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... NXP Semiconductors 4. Functional diagram OE1 1 OE2 19 Fig 1. Logic symbol 5. Pinning information 5.1 Pinning 74LV541 OE1 GND 10 001aaj964 Fig 3. Pin configuration DIP20, SO20 74LV541_3 Product data sheet mna900 Fig OE2 Fig 4. Rev. 03 — 14 April 2009 74LV541 Octal buffer/line driver; 3-state 1 & ...
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... NXP Semiconductors 5.2 Pin description Table 2. Pin description Symbol Pin OE1 GND 18, 17, 16, 15, 14, 13, 12, 11 data output OE2 Functional description [1] Table 3. Functional table Control OE1 OE2 [ HIGH voltage level LOW voltage level don’t care high-impedance OFF-state. 7. Limiting values Table 4. ...
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... NXP Semiconductors 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter [1] V supply voltage CC V input voltage I V output voltage O T ambient temperature amb t/ V input transition rise and fall rate [1] The static characteristics are guaranteed from ...
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... NXP Semiconductors Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter I supply current CC I additional supply current CC C input capacitance I [1] Typical values are measured at T 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see ...
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... NXP Semiconductors Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Symbol Parameter Conditions C power dissipation capacitance V = GND [1] All typical values are measured the same as t and PLH PHL t is the same as t and PZL PZH ...
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... NXP Semiconductors OEn input output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF OFF-to-HIGH Measurement points are given in V and V are typical voltage output levels that occur with the output load Fig 6. enable and disable times Table 8. Measurement points Supply voltage Input < 2.7 V 0. ...
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... NXP Semiconductors Test data is given in Table Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to output impedance External voltage for measuring switching times. EXT Fig 7. Test circuit for measuring switching times Table 9. Test data ...
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... NXP Semiconductors 12. Package outline DIP20: plastic dual in-line package; 20 leads (300 mil pin 1 index 1 DIMENSIONS (inch dimensions are derived from the original mm dimensions UNIT max. min. max. mm 4.2 0.51 3.2 inches 0.17 0.02 0.13 Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. ...
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... NXP Semiconductors SO20: plastic small outline package; 20 leads; body width 7 pin 1 index 1 e DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT max. 0.3 2.45 2.65 mm 0.25 0.1 2.25 0.012 0.096 0.1 inches 0.01 0.004 0.089 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. ...
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... NXP Semiconductors SSOP20: plastic shrink small outline package; 20 leads; body width 5 pin 1 index 1 e DIMENSIONS (mm are the original dimensions) A UNIT max. 0.21 1. 0.25 0.05 1.65 Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION IEC SOT339-1 Fig 10. Package outline SOT339-1 (SSOP20) ...
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... NXP Semiconductors TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4 pin 1 index 1 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 0.95 mm 1.1 0.25 0.05 0.80 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. ...
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... Document ID Release date 74LV541_3 20090414 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name when appropriate. 74LV541_2 19980610 74LV541_1 19970304 74LV541_3 ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Functional description . . . . . . . . . . . . . . . . . . . 3 7 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9 13 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 13 14 Revision history ...