74ALVCH162827DGG,1 NXP Semiconductors, 74ALVCH162827DGG,1 Datasheet - Page 2

• Manufacturer Part Number: 74ALVCH162827DGG,1
• Description: IC BUFF DVR TRI-ST 20BIT 56TSSOP
• Manufacturer: NXP Semiconductors
• Series: 74ALVCHr

Specifications of 74ALVCH162827DGG,1

• Package / Case: 56-TSSOP
• Logic Type: Buffer/Line Driver, Non-Inverting
• Number Of Elements: 2
• Number Of Bits Per Element: 10
• Current - Output High, Low: 12mA, 12mA
• Voltage - Supply: 2.3 V ~ 2.7 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Logic Family: ALVC
• Number Of Channels Per Chip: 20
• Polarity: Non-Inverting
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• High Level Output Current: - 12 mA
• Input Bias Current (max): 40 uA
• Low Level Output Current: 12 mA
• Minimum Operating Temperature: - 40 C
• Output Type: 3-State
• Propagation Delay Time: 3.1 ns (Typ) @ 2.7 V or 2.9 ns (Typ) @ 3.3 V
• Number Of Lines (input / Output): 20 / 20
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 74ALVCH162827DG-T; 74ALVCH162827DG-T; 935254370118

1.
Philips Semiconductors
FEATURES
QUICK REFERENCE DATA
GND = 0V; T
NOTES:
ORDERING INFORMATION
PIN DESCRIPTION
56-Pin Plastic TSSOP Type II
1998 Sep 29
Complies with JEDEC standard no. 8-1A.
CMOS low power consumption
Direct interface with TTL levels
Current drive
MULTIBYTE
Low inductance multiple V
and ground bounce
Integrated 30 W termination resistors
20-bit buffer/line driver, non-inverting, with 30
termination resistors (3-State)
t
C
C
C
PHL
SYMBOL
I
PD
PD
C
P
f
f
S (C
55, 54, 52, 51, 49, 48, 47, 45, 44, 43,
i
o
42, 41, 40, 38, 37, 36, 34, 33, 31, 30
15, 16, 17, 19, 20, 21, 23, 24, 26, 27
D
PD
= input frequency in MHz; C
/t
= output frequency in MHz; V
PLH
= C
2, 3, 5, 6, 8, 9, 10, 12, 13, 14,
L
is used to determine the dynamic power dissipation (P
4, 11, 18, 25, 32, 39, 46, 53
PD
amb
PACKAGES
V
CC
TM
PIN NUMBER
= 25 C; t
V
2
7, 22, 35, 50
12 mA at 3.0 V
flow-through standard pin-out architecture
Propagation delay
nAn to nYn
Input capacitance
Power dissipation capacitance per latch
Power dissi ation ca acitance er latch
CC
f
28, 29
1, 56,
2
o
) = sum of outputs.
f
i
r
+ S (C
= t
CC
f
= 2.5ns
and GND pins for minimum noise
L
PARAMETER
L
= output load capacity in pF;
V
CC
CC
TEMPERATURE RANGE
= supply voltage in V;
2
f
–40 C to +85 C
o
) where:
1OE1 1OE2,
2OE1, 2OE2
1A0 - 1A9
2A0 - 2A9
1Y0 - 1Y9
2Y0 - 2Y9
SYMBOL
GND
V
D
CC
V
V
V
V
in mW):
CC
CC
I
I
= GND to V
= GND to V
OUTSIDE NORTH AMERICA
= 2.5V, C
= 3.3V, C
2
74ALVCH162827DGG
DESCRIPTION
The 74ALVCH162827 high-performance CMOS device combines
low static and dynamic power dissipation with high speed and high
output drive.
The 74ALVCH162827 20-bit buffers provide high performance bus
interface buffering for wide data/address paths or buses carrying
parity. They have NAND Output Enables (nOE1, nOE2) for
maximum control flexibility.
The 74ALVCH162827 is designed with 30 series resistance in both
the pull-up and pull-down output structures. This design reduces line
noise in applications such as memory address drivers, clock drivers
and bus receivers/transmitters.
To ensure the high impedance state during power up or power
down, OE should be tied to V
minimum value of the resistor is determined by the
current-sinking/current-sourcing capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data
inputs at a valid logic level.
L
L
CC
CC
= 30pF
= 50pF
1
1
CONDITIONS
Data inputs
Data outputs
Output enable inputs (active-LOW)
Ground (0V)
Positive supply voltage
Output disabled
Output enabled
NORTH AMERICA
ACH162827DGG
CC
FUNCTION
through a pullup resistor; the
74ALVCH162827
TYPICAL
Product specification
2.9
2.9
14
5
3
DWG NUMBER
853-2127 20100
SOT364-1
UNIT
pF
pF
ns
F