74ALVCH16827DGG,11 NXP Semiconductors, 74ALVCH16827DGG,11 Datasheet - Page 2

• Manufacturer Part Number: 74ALVCH16827DGG,11
• Description: IC BUFF DVR TRI-ST 20BIT 56TSSOP
• Manufacturer: NXP Semiconductors
• Series: 74ALVCHr

Specifications of 74ALVCH16827DGG,11

• Package / Case: 56-TSSOP
• Logic Type: Buffer/Line Driver, Non-Inverting
• Number Of Elements: 2
• Number Of Bits Per Element: 10
• Current - Output High, Low: 24mA, 24mA
• Voltage - Supply: 1.2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Logic Family: ALVC
• Number Of Channels Per Chip: 20
• Polarity: Non-Inverting
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 2.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• High Level Output Current: - 24 mA
• Input Bias Current (max): 40 uA
• Low Level Output Current: 24 mA
• Minimum Operating Temperature: - 40 C
• Output Type: 3-State
• Propagation Delay Time: 2.1 ns (Typ) @ 2.7 V or 2 ns (Typ) @ 3.3 V
• Number Of Lines (input / Output): 20 / 20
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 74ALVCH16827DG-T; 74ALVCH16827DG-T; 935254390118

1.
Philips Semiconductors
FEATURES
QUICK REFERENCE DATA
GND = 0V; T
NOTES:
ORDERING INFORMATION
PIN DESCRIPTION
56-Pin Plastic TSSOP Type II
1998 Jul 27
Wide supply voltage range of 1.2V to 3.6V
Complies with JEDEC standard no. 8-1A
Wide supply voltage range of 1.2V to 3.6V
CMOS low power consumption
Direct interface with TTL levels
Universal bus transceiver with D-type latches and D-type flip-flops
capable of operating in transparent, latched, clocked or
clocked-enabled mode.
MULTIBYTE
Low inductance multiple V
and ground bounce
Current drive 24 mA at 3.0 V
All inputs have bus hold circuitry
Output drive capability 50 transmission lines @ 85 C
3-State non-inverting outputs for bus oriented applications
20-bit buffer/line driver, non-inverting (3-State)
t
C
C
C
PHL
SYMBOL
I
PD
PD
C
P
f
f
S (C
55, 54, 52, 51, 49, 48, 47, 45, 44, 43,
i
o
42, 41, 40, 38, 37, 36, 34, 33, 31, 30
15, 16, 17, 19, 20, 21, 23, 24, 26, 27
D
PD
= input frequency in MHz; C
/t
= output frequency in MHz; V
PLH
= C
2, 3, 5, 6, 8, 9, 10, 12, 13, 14,
L
is used to determine the dynamic power dissipation (P
4, 11, 18, 25, 32, 39, 46, 53
PD
amb
PACKAGES
V
CC
TM
PIN NUMBER
= 25 C; t
V
2
7, 22, 35, 50
flow-through standard pin-out architecture
Propagation delay
CP to Qn
Input capacitance
Power dissipation capacitance per latch
Power dissi ation ca acitance er latch
CC
f
28, 29
1, 56,
2
o
) = sum of outputs.
f
i
r
+ S (C
= t
CC
f
= 2.5ns
and GND pins for minimum noise
L
PARAMETER
L
= output load capacity in pF;
V
CC
CC
TEMPERATURE RANGE
= supply voltage in V;
2
f
–40 C to +85 C
o
) where:
1OE0, 1OE1
2OE0, 2OE1
1A0 - 1A9
2A0 - 2A9
1Y0 - 1Y9
2Y0 - 2Y9
SYMBOL
GND
V
D
CC
V
V
V
V
in mW):
CC
CC
I
I
= GND to V
= GND to V
OUTSIDE NORTH AMERICA
= 2.5V, C
= 3.3V, C
2
74ALVCH16827 DGG
DESCRIPTION
The 74ALVCH16827 is a 20-bit non-inverting buffer/driver with
3-State outputs for bus oriented applications.
The 74ALVCH16827 consists of two 10-bit sections with separate
output enable signals. For either 10-bit buffer section, the two output
enable (1OE1 and 1OE2 or 2OE1 and 2OE2) inputs must both be
active. If either output enable input is high, the outputs of that 10-bit
buffer section are in high impedance state.
The 74ALVCH16827 has active bus hold circuitry which is provided
to hold unused or floating data inputs at a valid logic level. This
feature eliminates the need for external pull-up or pull-down
resistors.
L
L
CC
CC
= 30pF
= 50pF
1
1
CONDITIONS
Data inputs
Data outputs
Output enable inputs (active-Low)
Ground (0V)
Positive supply voltage
Output disabled
Output enabled
NORTH AMERICA
ACH16827 DGG
FUNCTION
74ALVCH16827
TYPICAL
Product specification
2.0
2.0
20
5
3
DWG NUMBER
853-2096 19785
SOT364-1
UNIT
pF
pF
ns
F