HFA3861AIN Intersil Corporation, HFA3861AIN Datasheet - Page 10
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HFA3861AIN
Manufacturer Part Number
HFA3861AIN
Description
Processor, Direct Sequence Spread Spectrum Base band Processor
Manufacturer
Intersil Corporation
Datasheet
1.HFA3861AIN.pdf
(37 pages)
carrier phases, but only one is sent. This sequence is then
modulated on the I and Q outputs. The initial phase
reference for the data portion of the packet is the phase of
the last bit of the header. At 11Mbps, one byte is used as
above where 6 bits are used to select one of 64 spread
sequences for a symbol and the other 2 are used to QPSK
modulate that symbol. Thus, the total possible number of
combinations of sequence and carrier phases is 256. Of
these only one is sent.
The bit rate Table 3 shows examples of the bit rates and the
symbol rates and Figure 7 shows the modulation schemes.
The modulator is completely independent from the
demodulator, allowing the PRISM baseband processor to be
used in full duplex operation.
Header/Packet Description
The HFA3861A is designed to handle packetized Direct
Sequence Spread Spectrum (DSSS) data transmissions.
The HFA3861A generates its own preamble and header
information. It uses two packet preamble and header
configurations. The first is backwards compatible with the
existing IEEE 802.11-1997 1 and 2Mbps modes and the
second is the optional shortened mode which maximizes
throughput at the expense of compatibility with legacy
equipment.
In the long preamble mode, the device uses a
synchronization preamble of 128 symbols along with a
header that includes four fields. The preamble is all 1's
(before entering the scrambler) plus a start frame delimiter
(SFD). The actual transmitted pattern of the preamble is
randomized by the scrambler. The preamble is always
transmitted as a DBPSK waveform (1Mbps). The duration of
the long preamble and header is 192µs.
In the short preamble mode, the modem uses a
synchronization field of 56 zero symbols along with an SFD
transmitted at 1Mbps. The short header is transmitted at
2Mbps. The synchronization preamble is all 0’s to distinguish
it from the long header mode and the short preamble SFD is
the time reverse of the long preamble SFD. The duration of
the short preamble and header is 96µs.
Start Frame Delimiter (SFD) Field (16 Bits) - This field is
used to establish the link frame timing. The HFA3861A will
not declare a valid data packet, even if it PN acquires,
unless it detects the SFD. The HFA3861A receiver is
programmed to time out searching for the SFD via CR 10
BITS 4 and 5. The timer starts counting the moment that
initial PN synchronization has been established on the
preamble.
The four fields for the header shown in Figure 8 are:
Signal Field (8 Bits) - This field indicates what data rate the
data packet that follows the header will be. The HFA3861A
receiver looks at the signal field to determine whether it
needs to switch from DBPSK demodulation into DQPSK, or
10
HFA3861A
CCK demodulation at the end of the preamble and header
fields.
Service Field (8 Bits) - The MSB of this field is used to
indicate the correct length when the length field value is
ambiguous at 11Mbps. See IEEE STD 802.11 for definition
of the other bits. These bits are not used by the HFA3861A.
Length Field (16 Bits) - This field indicates the number of
microseconds it will take to transmit the payload data
(PSDU). The external controller (MAC) will check the length
field in determining when it needs to de-assert RX_PE.
CCITT - CRC 16 Field (16 Bits) - This field includes the 16-
bit CCITT - CRC 16 calculation of the three header fields.
This value is compared with the CCITT - CRC 16 code
calculated at the receiver. The HFA3861A receiver will
indicate a CCITT - CRC 16 error via CR24 bit 2 and will
lower MD_RDY and reset the receiver to the acquisition
mode if there is an error.
The CRC or cyclic Redundancy Check is a CCITT CRC-16
FCS (frame check sequence). It is the ones compliment of
the remainder generated by the modulo 2 division of the
protected bits by the polynomial:
x
The protected bits are processed in transmit order. All CRC
calculations are made prior to data scrambling. A shift
register with two taps is used for the calculation. It is preset
to all ones and then the protected fields are shifted through
the register. The output is then complemented and the
residual shifted out MSB first.
The following Configuration Registers (CR) are used to
program the preamble/header functions, more programming
details about these registers can be found in the Control
Registers section of this document:
CR 4 - Defines the preamble length minus the SFD in
symbols. The 802.11 protocol requires a setting of
128d = 80h for the mandatory long preamble and 56d = 38h
for the optional short preamble.
CR 10 Bits 4, 5 - Define the length of time that the
demodulator searches for the SFD before returning to
acquisition.
CR 5 Bits 0, 1 - These bits of the register set the Signal field
to indicate what modulation is to be used for the data portion
of the packet.
CR 6 - The value to be used in the Service field.
CR 7 and 8 - Defines the value of the transmit data length
field. This value includes all symbols following the last
header field symbol and is in microseconds required to
transmit the data at the chosen data rate.
The packet consists of the preamble, header and MAC
protocol data unit (MPDU). The data is transmitted exactly
16
+ x
12
+ x
5
+ 1