SD1010-1199A N/A, SD1010-1199A Datasheet - Page 11

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SD1010-1199A

Manufacturer Part Number
SD1010-1199A
Description
Analog-Interface XGA TFT LCD Display Controller
Manufacturer
N/A
Datasheet
November, 1999
Revision B
SmartASIC, Inc.
CLK_1M_O
PWM_CTL
HSYNC_X
SCAN_EN
CPU_SDA
RESET_B
TEST_EN
CLK_1M
EN_OSD
G_OSD
R_OSD
B_OSD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
100
106
128
101
124
113
118
112
114
10
31
11
12
13
14
15
16
26
41
52
62
76
77
84
94
25
36
46
56
57
67
68
79
89
99
5
6
7
9
8
3
SmartASIC Confidential
I/O SDA in I
O
O
O
I
I
I
I
I
I
I
I
PWM control signal (Detail description in PWM
Operation Section)
Free Running Clock (default: 1MHz)
Feedback of free Running Clock
System Reset ( active LOW)
Default HSYNC generated by ASIC (active LOW)
OSD Color Red
OSD Color Green
OSD Color Blue
OSD Mixer Enable
=0, No OSD output
=1,R_OUT[7:0]= {R_OSD repeat 8 times}
Manufacturing test pin (NC)
Manufacturing test pin (NC)
Power Supply
Power Supply
Power Supply
Power Supply
Power Supply
Power Supply
Power Supply
Power Supply
Power Supply
Power Supply
Power Supply
Power Supply
Power Supply
Power Supply
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
G_OUT[7:0]= {G_OSD repeat 8 times }
B_OUT[7:0]= {B_OSD repeat 8 times }
2
C for CPU interface
SD1010A
11

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