SD1010-1199A N/A, SD1010-1199A Datasheet - Page 39

• Manufacturer Part Number: SD1010-1199A
• Description: Analog-Interface XGA TFT LCD Display Controller
• Manufacturer: N/A

3.7.
When SD1010A is powered up, the reference system and SD1010A will perform the
following functions in sequence:
1. System will generate a Power-On Reset to SD1010A.
2. Once the SD1010A receives the Reset, SD1010A will load the contents of
November, 1999
Revision B
SmartASIC, Inc.
Agc_offset_green
Non_full_screen
ICS_hsize_value
Agc_gain_green
Agc_offset_blue
ICS_hsize_valid
Agc_offset_red
Agc_gain_blue
ICS_freq_state
Agc_gain_red
Divisor_value
Divisor_valid
ICS_iq_valid
Rom_clk_sel
EEPROM and start the auto-calibration process.
Input_max
Input_min
IQ_value
Panel_on
IQ_valid
Agc_en
Control Flow
11
30
11
1
8
8
8
8
8
8
8
8
1
1
1
1
1
1
1
6
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
R
R
R
R
SmartASIC Confidential
6AH,6BH,
6CH
69H[5:0],
6EH[2:0],
66H[5]
66H[4]
66H[3]
66H[2]
66H[1]
66H[0]
67H[2:0],
6DH[0]
70H[5:0] Divisor value use to divide fast pwm_free_clk to
5DH[0]
68H
5EH
5FH
60H
61H
62H
63H
64H
65H
6FH
0: disable detection
1: detect MAX/MIN using R color
2: detect MAX/MIN using G color
3: detect MAX/MIN using B color
Automatic gain control enable
Gain amount for R color
Gain amount for G color
Gain amount for B color
Offset amount for R color
Offset amount for G color
Offset amount for B color
Detected maximum input data (please see 5DH)
Detected minimum input data (please see 5DH)
Forces auto calibration to calculate the hsize value for a
particular clock frequency when supplied by ics chips
Indicates when hsize value is ready for cpu to read in
ics mode. Can be clear by cpu
Indicates when image quality is ready for cpu to read in
ics mode. Can be clear by cpu
Indicates when image quality is ready for cpu to read in
Regular non-ics mode. Can be clear by cpu
Indicates when auto clock frequency calibration is done
and frequency value is ready for cpu to read. Can be
clear by cpu
Indicates when input data is non full screen. Can be
clear by cpu
Read only register containing value of clock frequency
when divisor_valid is asserted
Read only register containing value of image quality
when either ics_iq_valid or iq_valid is asserted
1: turn on all the outputs to the panel
0: disable outputs to the panel (need to disable
EEPROM 265H[3], 266H[7], 266H[3], 267H[7],
267H[3] to get complete output disable).
Read only register containing value of hsize when
ics_hsize_valid is asserted
slower free_clk
SD1010A
39