SD1010-1199A N/A, SD1010-1199A Datasheet - Page 31

• Manufacturer Part Number: SD1010-1199A
• Description: Analog-Interface XGA TFT LCD Display Controller
• Manufacturer: N/A

The default device ID for the SD1010A is fixed “1111111”. The device ID can be
programmed through EEPROM entry 200H bit 0 through bit 6. This avoids any
conflict with other 2-wire serial devices on the same bus.
The following table briefly describes the SD1010A control registers. The external
CPU can read these registers to know the state of the SD1010A as well as the result of
input mode detection and phase calibration. The external CPU can modify these
control registers to disable several SD1010A features and force the SD1010A into a
particular state. When the CPU modifies the control registers, the new data will be
first stored in a set of shadow registers, and then copied into the actual control
registers when the “CPU Control Enable” bit is set. When the “CPU Control Enable”
bit is set, the external CPU will retain control and the SD1010A will not perform the
auto mode detection and auto calibration.
The external CPU is able to adjust the size of the output image and move the output
image up and down by simply changing the porch size and pixel and line numbers of
the input signal. These adjustments can be tied to the external user control button on
the monitor.
A set of four control registers are used to generate output signal when there is no input
signal available to the SD1010A or the input signal is beyond the acceptable ranges.
This operation mode is called standalone mode, which is very important for the end
users when they accidentally select an input mode beyond the acceptable range of the
SD1010A or when the input cable connection becomes loose for any reason. System
manufacturers can display appropriate OSD warning messages on the LCD panel to
notify the users about the problem.
Table 3: SD1010A Control Registers
November, 1999
Revision B
SmartASIC, Inc.
VTOTAL Source
HTOTAL Source
VSIZE Source
HSIZE Source
Mode Source
VBP Source
HBP Source
Symbol
Width Mode
11
11
11
11
11
11
4
RW
RW
RW
RW
RW
RW
RW
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CH[3:0] Input video format
AH-BH Input total number of pixels per line including porches
0H-1H
2H-3H
4H-5H
6H-7H
8H-9H
Input VSYNC back porch (not include pulse width)
Input image lines per frame
Input total number of lines including porches
Input HSYNC back porch (not include pulse width)
Input image pixels per line
0: 640x350
1: 640x400
2: 720x400
3: 640x480
4: 800x600
5: 832x624
6: 1024x768
7: user defined mode 1
8: user defined mode 2
9: user defined mode 3
10: user defined mode 4
Description
SD1010A
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