CC2420 Chipcon AS, CC2420 Datasheet - Page 26

• Manufacturer Part Number: CC2420
• Description: 2.4 GHz RF Transceiver for IEEE 802.15.4 and ZigBee
• Manufacturer: Chipcon AS

The RAM/Register bit must be set high to
enable RAM access. The 9 bit RAM
address consists of two parts, B1:0 (MSB)
selecting one of the three memory banks
and A7:0 (LSB) selecting the address
within the selected bank. The RAM is
divided into three memory banks: TXFIFO
(bank 0), RXFIFO (bank 1) and security
(bank 2). The FIFO banks are 128 bytes
each, while the security bank is 112 bytes.
A6:0 is transmitted directly after the
RAM/Register bit as shown in Figure 8.
For RAM access, a second byte is also
required before the data transfer. This
byte contains B1:0 in bits 7 and 6,
followed by the R/W bit (0 for read+write, 1
for read). Bits 4 through 0 are don’t care
as shown in Figure 8.
For RAM write, data to be written must be
input on the SI pin directly after the
Chipcon AS SmartRF® CC2420 Preliminary Datasheet (rev 1.0), 2003-11-17
Read or write a whole register (16 bit):
Read or write n bytes from/to RF FIFO:
Read or write n bytes from/to RAM:
Multiple command strobes:
Multiple register read or write
Read 8 MSB of a register:
Figure 9. Configuration registers write and read operations via SPI
Command strobe:
CSn:
Note:
FIFO and RAM access must be termiated with setting the CSn pin high.
Command strobes and register access may be followed by any other access,
since they are completed on the last negative edge on SCLK. They may however also be terminated
with setting CSn high, if desirable, e.g. for reading only 8 bits from a configuration register.
ADDRL
ADDR
ADDR
ADDR
ADDR
ADDR
ADDR
FIFO
RAM
ADDRH
DATA
DATA
DATA
DATA
ADDR
8MSB
8MSB
8MSB
byte0
RAM
DATA
DATA
DATA
DATA
ADDR
SmartRF
ADDR
8LSB
8LSB
byte1
second address byte. RAM data read is
output on the SO pin simultaneously, but
may be ignored by the user if only writing
is of interest.
For RAM read, the selected byte(s) are
output on the SO pin directly after the
second address byte.
See Figure 9 for an illustration on how
multiple RAM bytes may be read or written
in one operation.
The RAM memory space is shown in
Table 6.
As with register data, data stored in RAM
will be retained during a programmed
power-down mode, but not when the
power-supply
disabling the voltage regulator using the
VREG_EN pin).
DATA
DATA
...
ADDR
ADDR+1
byte2
DATA
DATA
DATA
ADDR+2
8MSB
byte3
is turned off (e.g. by
...
...
...
®
DATA
ADDR
byte n-3
CC2420
...
DATA
DATA
ADDR
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byte n-2
8MSB
DATA
DATA
DATA
ADDR
ADDR+n
byte n-1
8LSB