A43E06321 AMIC Technology, Corp., A43E06321 Datasheet
A43E06321
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A43E06321 Summary of contents
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... Preliminary 512K X 32 Bit X 2 Banks Low Power Synchronous DRAM Document Title 512K X 32 Bit X 2 Banks Low Power Synchronous DRAM Revision History Rev. No. History 0.0 Initial issue PRELIMINARY (July, 2005, Version 0.0) A43E06321 Issue Date Remark July 21, 2005 Preliminary AMIC Technology, Corp. ...
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... NC NC CKE CAS DQ VSS VDD VDDQ VSSQ VDDQ DQ VSS VDD 15 1 A43E06321 high performance memory VSSQ VDDQ 20 DQ VDDQ 18 DQ VSSQ 16 VDD DQM RAS DQM 0 WE ...
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... ADD LRAS LRAS LCBR CLK PRELIMINARY (July, 2005, Version 0.0) Data Input Register 512K X 32 512K X 32 Column Decoder Latency & Burst Length Programming Register LCAS LWE Timing Register CKE CS RAS CAS 2 A43E06321 DQM LWCBR DQM WE AMIC Technology, Corp. LWE DQM DQi ...
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... Enables write operation and Row precharge. Makes data output Hi-Z, t SHZ after the clock and masks the output. Blocks data input when DQM active. Data inputs/outputs are multiplexed on the same pins. Power Supply: +1.7V ~ 1.95V/Ground Provide isolated Power/Ground to DQs for improved noise immunity. 3 A43E06321 AMIC Technology, Corp. ...
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... VDDQ - 0 -1.5 OL See Fig. 1 (Page 6) 4 Min 2.0 CAS DQM 2.0 3.5 =-40ºC to +85ºC for extended) A Max Unit 1. VDDQ+0 0 0.2 V µ µ 1.5 AMIC Technology, Corp. A43E06321 Max Unit 4.0 pF 4.0 pF 6.0 pF Note Note -0.1mA 0.1mA OL Note 2 Note 3 ...
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... IH CC Input signals are changed one time during 30ns I = 0mA, Page Burst OL All bank Activated (min) CCD CCD ≥ (min CKE ≤ 0.2V CKE ≤ 0.2V 5 A43E06321 Value Unit µ F 0.1 + 0.01 µ F 0.1 + 0.01 = -40ºC to +85ºC for extended) A Speed -75 -95 40 0.3 0.5 5.5 = ∞ 2 1.5 ...
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... See Fig.2 1.8V V (DC) = VDDQ-0.2V -0.1mA OH OH 13.9KΩ V (DC) = 0.2V 0.1mA OL OL 30pF -75 Min CL=3 7.5 CL=2 12 CL CL=3 2.5 CL=2 2.5 CL=3 2.5 CL=2 2.5 CL CL A43E06321 Value V =0.5V x VDDQ TT 50Ω Z =50Ω OUTPUT O 30pF (Fig Output Load Circuit -95 Max Min Max 9.5 1000 1000 ...
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... CCD(min) Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. PRELIMINARY (July, 2005, Version 0.0) Parameter 7 A43E06321 Version Unit -75 - ...
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... Valid Don’t Care Logic High Logic Low) 8 A43E06321 WE DQM BA A10 A9~A0 / CODE CODE Row Addr. L Column Addr ...
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... Reserved Reserved Reserved ↓ ↓ ↓ ↓ Bank DS 0 Up/Down A43E06321 CAS Latency BT Burst Length Type BT=0 Sequential Interleave Reserved ...
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... A43E06321 Interleave Interleave ...
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... Register must be programmed with A8 through A10 set to “0”. The Extended Mode Register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time initiating any subsequent operation. Violating either of these requirements results in unspecified operation. 11 A43E06321 WE CAS , BA in the ...
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... The minimum number of clock cycles required to complete row precharge is calculated by dividing “t time and rounding up to the next higher integer. Care should 12 A43E06321 WE CAS with being high on the positive edge of CS ” ...
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... To with high on CKE enter the Deep Power Down Mode all banks must be precharged and the necessary Precharged Delay t occur. 13 A43E06321 (min)”. The minimum number of clock cycles RC ” with clock cycle RC RAS ...
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... DQM makes data out Hi-Z after 2 clocks which should masked by CKE “L”. 2. DQM masks both data-in and data-out. PRELIMINARY (July, 2005, Version 0.0) 2) Clock Suspended During Read (BL= Read Mask (BL=4) RD Hi-Z Hi Hi-Z Hi A43E06321 Masked by CKE Suspended Dout Masked by CKE Hi Hi DQM to Data-out Mask = 2 Hi-Z ...
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... Last data in to new column address delay. (= 1CLK). CDL PRELIMINARY (July, 2005, Version 0.0) Note 1 QB0 QB1 QB2 QB3 QA0 QB0 QB1 QB2 QB3 DQ(CL2) DQ(CL3) CAS access; read, write and block write. 15 A43E06321 3) Write interrupted by Read (BL = CCD Note2 A B DA0 QB0 QB1 DA0 QB0 t CDL Note3 AMIC Technology, Corp ...
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... To prevent bus contention, DQM should be issued which makes a least one gap between data in and data out. PRELIMINARY (July, 2005, Version Note Hi Hi Note 2 16 A43E06321 AMIC Technology, Corp. ...
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... Version 0.0) Note 2 PRE Note Masked by DQM PRE RDL PRE Note 1 Auto Precharge Starts Note 1 Auto Precharge Starts CAS interrupt of the same/another bank is illegal. 17 A43E06321 from this point. RP AMIC Technology, Corp. ...
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... Version 0.0) 2) Write Burst Stop (BL=8) PRE Note 1 RDL 4) Read Burst Stop (BL=4) PRE Note DQ(CL2 DQ(CL3) MRS ACT t 1CLK RP 18 A43E06321 CLK CMD WR STOP (note 2) BDL CLK CMD RD STOP AMIC Technology, Corp. Note ...
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... Version 0.0) 2) Power Down (=Precharge Power Down) Exit AUTO REFRESH commands must be issued every 15.6 μ less as both SELF 19 CLK CKE t SS Internal Note 2 CLK NOP ACT CMD Note 5 CMD CMD t RC AMIC Technology, Corp. A43E06321 ...
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... During read/write burst with auto precharge, RAS interrupt cannot be issued. Before the end of burst, new read/write stops read/write burst and starts new read/write burst or block write. During read/write burst with auto precharge, 20 A43E06321 CAS interrupt can not be issued. AMIC Technology, Corp. ...
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... DQM High level is necessary High Precharge Auto Refresh (All Banks) PRELIMINARY (July, 2005, Version 0. Auto Refresh 21 A43E06321 KEY KEY t RC Normal Extended MRS MRS AMIC Technology, Corp Row Active (A-Bank) : Don't care ...
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... *Note 2,3 *Note 2 *Note 3 *Note SAC SLZ SHZ Read Write 22 A43E06321 *Note 4 *Note *Note Row Active Precharge AMIC Technology, Corp Don't care ...
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... Disable auto precharge, leave bank A active at end of burst. 1 Disable auto precharge, leave bank B active at end of burst. 0 Enable auto precharge, precharge bank A at end of burst. 1 Enable auto precharge, precharge bank B at end of burst. BA Precharge 0 Bank A 1 Bank B X Both Bank 23 A43E06321 AMIC Technology, Corp. ...
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... OH Qa0 Qa1 Qa2 Qa3 *Note SHZ SAC Precharge Row Active (A-Bank) (A-Bank) from the clock. SHZ *(t + CAS latency- RCD SAC 24 A43E06321 Cb0 Db0 Db1 Db2 Db3 t RDL Db0 Db1 Db2 Db3 t RDL Write Precharge (A-Bank) AMIC Technology, Corp ...
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... High Cb0 Cc0 *Note 2 *Note1 Qa0 Qa1 Qb0 Qb1 Dc0 Qa0 Qa1 Qb0 Dc0 Write Read (A-Bank) (A-Bank) before Row precharge, will be written. RDL 25 A43E06321 *Note 2 Cd0 t RDL t CDL *Note3 Dc1 Dd0 Dd1 Dc1 Dd0 Dd1 Write Precharge ...
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... QBb0 QBb1 QAa0 QAa1 QAa2 QAa3 QBb0 Read (B-Bank) WE CAS RAS , and are high at the clock high going edge. 26 A43E06321 CAc CBd CAe QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1 ...
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... PRELIMINARY (July, 2005, Version 0. High RBb CBb RBb DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 t CDL Write (B-Bank) (B-Bank) 27 A43E06321 *Note 2 CAc CBd DAc1 DBd0 DBd1 t RDL *Note 1 Precharge Write (Both Banks) (A-Bank) Write (B-Bank) AMIC Technology, Corp. ...
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... High RBb RBb QAa0 QAa1 QAa2 QAa3 QAa0 QAa1 QAa2 QAa3 Precharge (A-Bank) Row Active (B-Bank) 28 A43E06321 CBb RAc CAc RAc t CDL *Note 1 DBb0 DBb1 DBb2 DBb3 DBb0 DBb1 DBb2 DBb3 Write Read (B-Bank) (A-Bank) ...
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... High CAa QAa0 QAa1 QAa2 QAa3 QAa0 QAa1 QAa2 QAa3 Auto Precharge Start Point (A-Bank) (A-Bank) 29 A43E06321 CBb DBb0 DBb1 DBb2 DBb3 DBb0 DBb1 DBb2 DBb3 Write with Auto Precharge Auto Precharge (B-Bank) AMIC Technology, Corp. ...
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... Auto Precharge Strart Point (A-Bank) *Note 1 after A Bank auto precharge starts Qb3 Qb2 Qb3 Precharge Row Active (B-Bank) (A-Bank) AMIC Technology, Corp. A43E06321 Da0 Da1 Da0 Da1 Write with Auto Precharge (A-Bank) : Don't care ...
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... Rb Qa0 Qa1 Qa2 Qa3 Qa0 Qa1 Qa2 Qa3 * Note 1 Auto Precharge Read with Auto Precharge Start Point (A-Bank) (B-Bank) Row Active (B-Bank) 31 A43E06321 Qb0 Qb1 Qb2 Qb3 Qb0 Qb1 Db2 Db3 Auto Precharge Start Point (B-Bank) AMIC Technology, Corp. ...
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... QAa1 QAa2 QAa3 QAa4 QAa0 QAa0 QAa1 QAa2 QAa3 QAa4 Read Burst Stop (A-Bank QAb0 QAb1 QAb2 QAb3 QAb4 QAb5 2 QAb0 QAb1 QAb2 QAb3 Precharge (A-Bank) RAS interrupt. AMIC Technology, Corp. A43E06321 QAb4 QAb5 : Don't care ...
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... Version 0. High CAb * Note 1 t BDL * Note 2 DAa1 DAa2 DAa3 DAa4 DAb0 DAb1 DAb2 DAb3 Write Burst Stop (A-Bank) 33 A43E06321 RDL * Note 3 DAb4 DAb5 AMIC Technology, Corp Precharge (A-Bank) : Don't care ...
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... High CAb RAc RAc QAb0 QAb1 QAb0 QAb1 Row Active (A-Bank) Read with Auto Precharge Auto Precharge (A-Bank) 34 A43E06321 Note 2 CBc CAd DBc0 QAd0 QAd1 DBc0 QAd0 Read Precharge (A-Bank) (A-Bank) Write with (B-Bank) AMIC Technology, Corp. ...
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... Row Active Read Suspension * Note : DQM needed to prevent bus contention. PRELIMINARY (July, 2005, Version 0. Qa0 Qa1 Qa2 Qa3 t SHZ Clock Read 35 A43E06321 Note 1 Qb0 Qb1 Dc0 Dc2 t SHZ Write DQM Read DQM Clock Write Suspension AMIC Technology, Corp ...
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... Version 0. Note Precharge Power-down Exit Row Active Active Active Power-down Power-down Exit Entry ” prior to Row active command A43E06321 Qa0 Qa1 Qa2 Read Precharge AMIC Technology, Corp Don't care ...
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... Before/After self refresh mode, AUTO REFRESH commands must be issued every 15.6μs or less as both SELF REFRESH and AUTO REFRESH utilize the row refresh counter. PRELIMINARY (July, 2005, Version 0. Note 4 * Note 3 Hi-Z Self Refresh Exit 37 A43E06321 min Note 6 * Note 5 * Note 7 Auto Refresh AMIC Technology, Corp. ...
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... Please refer to Mode Register Set table. PRELIMINARY (July, 2005, Version 0.0) Auto Refresh Cycle Auto Refresh WE activation at the same clock cycle with address key will set internal mode register. RAS activation. 38 A43E06321 High t RC Hi-Z AMIC Technology, Corp ...
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... Deep Power Down Mode Entry CLK CKE CS WE CAS RAS ADDR DQM DQ input DQ output PRELIMINARY (July, 2005, Version 0.0) High Precharge Command Deep Power Down Entry Normal Mode Deep Power Down Mode 39 A43E06321 AMIC Technology, Corp. ...
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... Issue a mode register set command to initialize the mode register 5. Issue an extended mode register set command to initialize the extended mode register PRELIMINARY (July, 2005, Version 0. All Banks Auto Precharge Refresh Refresh Mode Extended Auto Register Mode Set Register Set AMIC Technology, Corp. A43E06321 New Command Accepted Here ...
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... NOP(Continue Burst to End → Precharge NOP(Continue Burst to End → Precharge ILLEGAL H BA CA,A10/AP ILLEGAL L BA CA,A10/AP ILLEGAL X BA RA, PA ILLEGAL ILLEGAL 41 A43E06321 Action Note AMIC Technology, Corp. ...
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... NOP → Idle after NOP → Idle after ILLEGAL ILLEGAL ILLEGAL BA = Bank Address CA = Column Address 42 A43E06321 Action RCD RCD Auto Precharge PA = Precharge All AMIC Technology, Corp. Note ...
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... Refer to Operations in Table Begin Clock Suspend next cycle Exit Clock Suspend next cycle Maintain clock Suspend 43 A43E06321 Action RC RC (min) has to be elapse after CKE’s low to RC AMIC Technology, Corp. Note ...
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... Note for industrial operating temperature range -40ºC to +85ºC. PRELIMINARY (July, 2005, Version 0.0) Max. Clock Frequency Access Time (MHz) 133 133 105 105 44 A43E06321 Package ball Pb-Free CSP ball Pb-Free CSP ball Pb-Free CSP ball Pb-Free CSP AMIC Technology, Corp. ...
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... Detail B Dimensions in inches Min Nom Max - - 0.055 0.012 0.014 0.016 0.033 0.035 0.037 0.013 0.014 0.016 0.311 0.315 0.319 0.508 0.512 0.516 - 0.252 - - 0.441 - - 0.031 - 0.016 0.018 0.020 0.004 0.004 0.005 0.006 0.003 9/15 AMIC Technology, Corp. A43E06321 unit: mm ...