CS61310-CL Cirrus Logic, Inc., CS61310-CL Datasheet - Page 15

• Manufacturer Part Number: CS61310-CL
• Description: Interface, T1 Line Interface Unit
• Manufacturer: Cirrus Logic, Inc.

LOOPUP
RPWDN
TxHIZ
RSVD
2.15
EQ[4:0]
2.16
RAM[7:0]
2.17
An interrupt will occur (INT pulls low) in response
to a change in the LOS, AIS or NLOOP bits. The in-
terrupt is cleared when the host processor writes a
“1” to the respective bit in the control register.
Writing a “1” to LOS or NLOOP over the serial in-
terface has three effects:
1)
2)
3)
Writing a “0” to either LOS or NLOOP enables the
corresponding interrupt for LOS and NLOOP.
Reading the registers returns their current status or
setting. Register 16 outputs the status NLOOP and
LOS and has bits 5, 6, and 7 encoded as shown in
Table 4.
Writing the arbitrary waveform RAM requires a de-
viation from normal serial port access. Register 19
DS440F1 FEB ‘03
7 (MSB)
7 (MSB)
RAM.7
The current interrupt on the serial interface
will be cleared. (Note that simply reading the
register bits will not clear the interrupt).
Output data bits 5, 6 and 7 will be reset as ap-
propriate.
Interrupts for the corresponding LOS and
NLOOP will be prevented from occurring.
X
Equalizer Gain (EQGAIN): Address 0x12
RAM Address (RAM): Address 0x13
Interrupts
RAM.6
Setting LOOPUP to “1” causes the data pattern 00001... to be repetitively transmitted.
When RPWDN = 1, the receiver circuitry is powered down, but the transmitter is still active.
When TxHIZ = 1 the transmitter goes to a low-power, high-impedance state
LSBs of this register, EQ4 - EQ0. 00001 corresponds to -2 dB, 10100 corresponds to -40 dB.
The three MSBs are don’t cares.
a special write procedure must be followed to write the waveform RAM.
Loop Up
Receiver Power Down
Transmitter High Impedance
Reserved. Set to 0 for proper operation.
The receive equalizer gain settings are broken down into 20 segments and provided at the five
The RAM address pointer for the arbitrary waveform memory;
X
6
6
RAM.5
X
5
5
RAM.4
EQ4
4
4
is the RAM address register for the arbitrary wave-
form. Two consecutive address bytes are written;
first the Address/Command Byte is written to ad-
dress 0x13, followed by the address in RAM to be
written. This dual address is then followed by the
data byte for the waveform amplitude. There are
42 RAM byte locations (numbered h00 to h29).
7
0
0
0
0
1
1
1
1
RAM.3
Bits
EQ3
6
0
0
1
1
0
0
1
1
3
3
5
0 Reset has occurred, or no program input
1 RLOOP active
0 LLOOP active
1 LOS has changed state since last Clear
0 TAOS active
1 NLOOP has changed state since last
0 TAOS and LLOOP active
1 LOS and NLOOP have both changed
LOS occurred
Clear NLOOP occurred
state since last Clear NLOOP and Clear
LOS
Table 4. Register 16 Decoding
RAM.2
EQ2
2
2
Status
RAM.1
EQ1
1
1
CS61310
0 (LSB)
0 (LSB)
RAM.0
EQ0
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