CS61535A Cirrus Logic, Inc., CS61535A Datasheet - Page 13

• Manufacturer Part Number: CS61535A
• Description: T1-E1 Line Interface Unit for PCM applications
• Manufacturer: Cirrus Logic, Inc.

120
110
100
When any transmit control pin (TAOS, LEN0-2
or LLOOP) is toggled, the transmitter stabilizes
within 22 bit periods. The transmitter will take
longer to stabilize when RLOOP is selected be-
cause the timing circuitry must adjust to the new
frequency.
Jitter Attenuator
The jitter attenuator is designed to reduce wander
and jitter in the transmit clock signal. It consists
of a 32 bit FIFO, a crystal oscillator, a set of load
capacitors for the crystal, and control logic. The
jitter attenuator exceeds the jitter attenuation re-
quirements of Publications 43802 and REC.
G.742. A typical jitter attenuation curve is shown
in Figure 10.
The jitter attenuator works in the following man-
ner. Data on TPOS and TNEG (or TDATA) are
written into the jitter attenuator’s FIFO by TCLK.
The rate at which data is read out of the FIFO and
transmitted is determined by the oscillator. Logic
circuits adjust the capacitive loading on the crys-
DS40F2
-10
-20
Figure 9 . Mask of the Pulse at the 2048 kbps Interface
90
80
50
10
0
Percent of
nominal
peak
voltage
269 ns
244 ns
194 ns
219 ns
488 ns
Nominal Pulse
tal to set its oscillation frequency to the average
of the TCLK frequency. Signal jitter is absorbed
in the FIFO.
Jitter Tolerance of Jitter Attenuator
The FIFO in the jitter attenuator is designed to
neither overflow nor underflow. If the jitter am-
plitude becomes very large, the read and write
pointers may get very close together. Should the
pointers attempt to cross, the oscillator’s divide
by four circuit adjusts by performing a divide by
3 1/2 or divide by 4 1/2 to prevent the overflow
or underflow. When a divide by 3 1/2 or 4 1/2
occurs, the data bit will be driven on to the line
either an eighth bit period early or an eighth bit
period late.
When the TCLK frequency is close to the center
frequency of the crystal oscillator, the high fre-
quency jitter tolerance is 23 UI before the divide
by 3 1/2 or 4 1/2 circuitry is activated. As the
center frequency of the oscillator and the TCLK
frequency deviate from one another, the jitter tol-
erance is reduced. As this frequency deviation
becomes large, the maximum jitter tolerance at
high frequencies is reduced to 12 UI before the
underflow/overflow circuitry is activated. In ap-
plication, it is unlikely that the oscillator center
frequency will be precisely aligned with the
10
20
30
40
50
60
0
Figure 10. Typical Jitter Attenuation Curve
1
b) Maximum
Attenuation
Limit
10
a) Minimum Attenuation Limit
100
Frequency in Hz
Requirements
AT&T 62411
Measured Performance
1 k
CS61535A
10 k
13