CS61535A Cirrus Logic, Inc., CS61535A Datasheet - Page 14

• Manufacturer Part Number: CS61535A
• Description: T1-E1 Line Interface Unit for PCM applications
• Manufacturer: Cirrus Logic, Inc.

TCLK frequency due to allowable TCLK toler-
ance, part to part variations, crystal to crystal
variations, and crystal temperature drift. The os-
cillator tends to track low frequency jitter so jitter
tolerance increases as jitter frequency decreases.
The crystal frequency must be 4 times the nomi-
nal signal frequency: 6.176 MHz for 1.544 MHz
operation; 8.192 MHz for 2.048 MHz applica-
tions. Internal capacitors load the crystal,
controlling the oscillation frequency. The crystal
must be designed so that over operating tempera-
ture, the oscillator frequency range exceeds the
system frequency tolerance. Crystal Semiconduc-
tor offers the CXT6176 & CXT8192 crystals,
which yield optimum performance with the
CS61535A.
Transmit All Ones Select
The transmitter provides for all ones insertion at
the frequency of ACLKI. Transmit all ones is se-
lected when TAOS goes high, and causes
continuous ones to be transmitted on the line
(TTIP and TRING). In this mode, the TPOS and
TNEG (or TDATA) inputs are ignored. A TAOS
request will be ignored if remote loopback is in
effect. ACLKI jitter will be attenuated. TAOS is
14
1 : 2
RTIP
RRING
Figure 11. Receiver Block Diagram
Detector
Slicer
Level
Edge
Data
not available on the CS61535A when ACLKI is
grounded.
Receiver
The receiver extracts data and clock from an AMI
(Alternate Mark Inversion) coded signal and out-
puts clock and synchronized data. The receiver is
sensitive to signals over the entire range of cable
lengths and requires no equalization or ALBO
(Automatic Line Build Out) circuits. The signal is
received on both ends of a center-tapped, center-
grounded transformer. The transformer is
center-tapped on the IC side. The clock and data
recovery circuit exceeds the jitter tolerance speci-
fications of Publications 43802, 43801, 62411
amended, TR-TSY-000170, and CCITT REC.
G.823.
A block diagram of the receiver is shown in Fig-
ure 11. The two leads of the transformer (RTIP
and RRING) have opposite polarity allowing the
receiver to treat RTIP and RRING as unipolar sig-
nals. Comparators are used to detect pulses on
RTIP and RRING. The comparator thresholds are
dynamically established at a percent of the peak
level (50% of peak for E1, 65% of peak for T1;
with the slicing level selected by LEN2/1/0).
Continuously
Delay Line
Calibrated
Extraction
Sampling
Selector
Phase
Clock
Clock
Data
&
RPOS
RNEG
RCLK
ACLKI or
Oscillator in Jitter
Attenuator
CS61535A
DS40F2