CS61535A Cirrus Logic, Inc., CS61535A Datasheet - Page 32

• Manufacturer Part Number: CS61535A
• Description: T1-E1 Line Interface Unit for PCM applications
• Manufacturer: Cirrus Logic, Inc.

ter the falling edge of TCLK. The CS61534 re-
quires 50 ns of hold time on TPOS and TNEG
after the falling edge of TCL, and 0 ns of setup
time.
6) LOS occurs after 31 consecutive zeros on the
CS61534. For the CS61535A LOS occurs after
175 zeros.
7) Since the CS61535A receivers are continu-
ously calibrated, there is no need to issue a reset
to initialize the receiver timing as with the
CS61534.
Using the CS61535A for SONET
The CS61535A can be applied to SONET VT1.5
and VT2.0 interface circuits as shown in Fig-
ure A5. The SONET data rate is 51.84 MHz, and
has 6480 bits per frame (125 us per frame). An
individual T1 frame (193 bits per frame) or PCM-
32
(or 256 bit)
Mapping
6480 to
193 bit
Circuit
TCLK1
RCLK1
TSER
RSER
51.84 MHz
Empty
FIFO
FIFO
Clock
Write
Div By
Figure A5. SONET Application
RCLK2
TSER
RSER
CS62180B
30 frame (256 bits per frame) has its data mapped
into the 6480 bit SONET frame. The mapping
does not result in a uniform spacing between
sucessive T1 (or E1) bits. Rather, for locked VT
applications, gaps as large as 24 T1 bit periods or
32 E1 bit periods can exist between successive
bits. With floating VTs, the gaps can be even
larger.
The circuit in Figure A5 eliminates the demulti-
plexing jitter in a two-step approach. The first
step uses a FIFO which is filled at a 51.84 MHz
rate (when T1 or E1 bits are present), and which
is emptied at a sub-multiple of the 51.84 rate. The
FIFO is emptied only when it contains data.
When the FIFO is empty the output clock is not
pulsed.
The sub-multiple rate chosen should be slightly
faster than the target rate (1.544 or 2.048 MHz),
but as close to the target rate as possible. For
TCLK2
TPOS
TNEG
RPOS
RNEG
RCLK2
Attenuator
Jitter
CS61535A
Receiver
Driver
CS61535A
DS40F2