P3Z22V10 NXP Semiconductors, P3Z22V10 Datasheet - Page 7

• Manufacturer Part Number: P3Z22V10
• Description: 3v Zero Power, Totalcmos, Universal Pld Device
• Manufacturer: NXP Semiconductors

Philips Semiconductors
Program/Erase Cycles
The P3Z22V10 is 100% testable, erases/programs in seconds, and
guarantees 1000 program/erase cycles.
Output Polarity
Each macrocell can be configured to implement Active-High or
Active-Low logic. Programmable polarity eliminates the need for
external inverters.
Output Enable
The output of each I/O macrocell can be enabled or disabled under
the control of its associated programmable output enable product
term. When the logical conditions programmed on the output enable
term are satisfied, the output signal is propagated to the I/O pin.
Otherwise, the output buffer is driven into the high-impedance state.
Under the control of the output enable term, the I/O pin can function
as a dedicated input, a dedicated output, or a bi-directional I/O.
Opening every connection on the output enable term will
permanently enable the output buffer and yield a dedicated output.
Conversely, if every connection is intact, the enable term will always
be logically FALSE and the I/O will function as a dedicated input.
Register Feedback Select
When the I/O macrocell is configured to implement a registered
function (S1 = 0) (Figures 3a or 3b), the feedback signal to the AND
array is taken from the Q output.
Bi-directional I/O Select
When configuring an I/O macrocell to implement a combinatorial
function (S1 = 1) (Figures 3c or 3d), the feedback signal is taken
Table 1. Typical I
V
1997 Jul 18
DD
Typical I
3V zero power, TotalCMOS , universal PLD device
FREQ (MHz)
= 3.3V@25 C
DD
(mA)
DD
I
(mA)
0.2
DD
1
vs. Frequency
30
25
20
15
10
5
0
1.5
10
Figure 4.
0
1
10
3.0
20
20
Typical I
4.5
30
30
DD
40
vs. Frequency @ V
6.0
40
50
FREQUENCY (MHz)
7.4
50
60
7
from the I/O pin. In this case, the pin can be used as a dedicated
input, a dedicated output, or a bi-directional I/O.
Power-On Reset
To ease system initialization, all flip-flops will power-up to a reset
condition and the Q output will be low. The actual output of the
P3Z22V10 will depend on the programmed output polarity. The V
rise must be monotonic.
Design Security
The P3Z22V10 provides a special EEPROM security bit that
prevents unauthorized reading or copying of designs programmed
into the device. The security bit is set by the PLD programmer,
either at the conclusion of the programming cycle or as a separate
step, after the device has been programmed. Once the security bit is
set, it is impossible to verify (read) or program the P3Z22V10 until
the entire device has first been erased with the bulk-erase function.
TotalCMOS
for Fast Zero Power
Philips is the first to offer a TotalCMOS SPLD, both in process
technology and design technique. Philips employs a cascade of
CMOS gates to implement its Sum of Products instead of the
traditional sense amp approach. This CMOS gate implementation
allows Philips to offer SPLDs which are both high performance and low
power, breaking the paradigm that to have low power, you must accept
low performance. Refer to Figure 4 and Table 1 showing the I
Frequency of our P3Z22V10 TotalCMOS
8.9
70
60
DD
= 3.3V, 25 C (10-bit counter)
80
10.4
70
90
11.8
Design Technique
80
100
110
13.2
90
120
14.5
100
130
TYPICAL
SPLD.
15.8
110
P3Z22V10
Product specification
17.0
120
SP00443
DD
18.2
130
vs.
CC