ATA6020N ATMEL Corporation, ATA6020N Datasheet - Page 10

• Manufacturer Part Number: ATA6020N
• Description: Low-current Microcontroller For Watchdog Function
• Manufacturer: ATMEL Corporation

4.1.7.2
Table 4-1.
Table 4-2.
4.1.7.3
4.1.7.4
10
Interrupt
Interrupt
ATA6020N
INT0
INT1
INT2
INT3
INT4
INT5
INT6
INT7
INT1
INT2
INT3
INT4
INT6
INT7
Interrupt Latency
Software Interrupts
Hardware Interrupts
Interrupt Priority Table
Hardware Interrupts
The interrupt latency is the time from the occurrence of the interrupt to the interrupt service rou-
tine being activated. This is extremely short (taking between 3 to 5 machine cycles depending
on the state of the core).
The programmer can generate interrupts by using the software interrupt instruction (SWI), which
is supported in qFORTH by predefined macros named SWI0...SWI7. The software triggered
interrupt operates exactly like any hardware triggered interrupt. The SWI instruction takes the
top two elements from the expression stack and writes the corresponding bits via the I/O bus to
the interrupt pending register. Therefore, by using the SWI instruction, interrupts can be re-prior-
itized or lower priority processes scheduled for later execution.
In the ATA6020N, there are eleven hardware interrupt sources with seven different levels. Each
source can be masked individually by mask bits in the corresponding control registers. An over-
view of the possible hardware configurations is shown in
Priority
highest
lowest
|
|
|
|
|
Register
P5CR
T2CM
P5CR
SISC
VCM
T1M
ROM Address
Interrupt Mask
0C0h
1C0h
040h
080h
100h
140h
180h
1E0h
P52M1, P52M2
P53M1, P53M2
P50M1, P50M2
P51M1, P51M2
D8h (SCALL 0C0h)
FCh (SCALL 1E0h)
C8h (SCALL 040h)
D0h (SCALL 080h)
F8h (SCALL 1C0h)
E8h (SCALL 100h)
E8h (SCALL 140h)
F0h (SCALL 180h)
Interrupt Opcode
T1IM
T2IM
SIM
VIM
Bit
Table 4-2 on page
Function
Software interrupt (SWI0)
External hardware interrupt, any
edge at BP52 or BP53
Timer 1 interrupt
SSI interrupt or external
hardware interrupt at BP40 or
BP43
Timer 2 interrupt
Software interrupt (SW15)
External hardware interrupt, at
any edge at BP50 or BP51
Voltage monitor (VM) interrupt
Interrupt Source
Any edge at BP52
Any edge at BP53
Timer 1
SSI buffer full/empty or
BP40/BP43 interrupt
Timer 2 compare match/overflow
Any edge at BP50
Any edge at BP51
External/internal voltage
monitoring
10.
4708D–4BMCU–09/05