ATA6020N ATMEL Corporation, ATA6020N Datasheet - Page 30

• Manufacturer Part Number: ATA6020N
• Description: Low-current Microcontroller For Watchdog Function
• Manufacturer: ATMEL Corporation

5.2.5.2
5.2.5.3
30
ATA6020N
Timer 1 Control Register 2 (T1C2)
Watchdog Control Register (WDC)
Bit 3 = MSB, Bit 0 = LSB
Bit 3 = MSB, Bit 0 = LSB
Both these bits control the time interval for the watchdog reset
Table 5-6.
Note:
T1C2
T1BP
T1CS
T1IM
WDC
WDL
WDR
WDT1
WDT0
WDT1
t
in
0
0
1
1
: input clock period = 1/C
WatchDog Lock mode
WDL = 1, the watchdog can be enabled and disabled by using the WDR-bit
WDL = 0, the watchdog is enabled and locked. In this mode the WDR-bit has no
WatchDog Run and stop mode
WDR = 1, the watchdog is stopped/disabled
WDR = 0, the watchdog is active/enabled
WatchDog Time 1
WatchDog Time 0
Bit 3
–
Timer 1 SUBCL ByPassed
T1BP = 1, TIOUT = T1MUX
T1BP = 0, T1OUT = SUBCL
Timer 1 input Clock Select
T1CS = 1, CL1 = SUBCL (see
T1CS = 0, CL1 = SYSCL (see
Timer 1 Interrupt Mask
T1IM = 1, disables Timer 1 interrupt
T1IM = 0, enables Timer 1 interrupt
Bit 3
WDL
Watchdog Time Control Bits
effect. After the WDL-bit is cleared, the watchdog is active until a system
reset or power-on reset occurs.
Bit 2
T1BP
Bit 2
WDR
WDT0
0
1
0
1
Bit 1
T1CS
in
Bit 1
WDT1
(see
Figure 4-12 on page
Figure 5-11 on page
Figure 5-11 on page
Bit 0
T1IM
Bit 0
WDT0
Divider
131072
16384
2048
512
Address: '7'hex – Subaddress: '9'hex
Reset value: x111b
Address: ’7’hex – Subaddress: ’A’hex
Reset value: 1111b
15)
33)
33)
Delay Time to Reset with
0.256 ms/0.512 ms
1.024 ms/2.048 ms
t
65.5 ms/131 ms
8.2 ms/16.4 ms
in
= 1/(2/1 MHz)
4708D–4BMCU–09/05