CDK1300 Cadeka Microcircuits LLC., CDK1300 Datasheet - Page 2

• Manufacturer Part Number: CDK1300
• Description: 8-bit, 250 Msps Adc With Demuxed Outputs
• Manufacturer: Cadeka Microcircuits LLC.

Data Sheet
Pin Configuration
TQFP-44
Pin Assignments
©2008 CADEKA Microcircuits LLC
38, 41, 44
1, 33, 34,
8, 18, 29
7, 17, 30
Pin No.
35, 36,
32, 31
42, 43
19-26
16-9
40
39
28
27
37
4
3
5
6
2
DMODE
Pin Name
DA
DB
DCLK
DCLK
RESET
RESET
AGND
DGND
OV
AV
V
V
CLK
CLK
V
0
0
PD
IN+
IN-
–DA
–DB
CM
CC
DD
OUT
OUT
1,2
7
7
CDK1300
Description
Non-inverted analog input; nominally 1V
Inverted analog input; nominally 1V
Data output bank A; 3V/5V LVCMOS compatible
Data output bank B; 3V/5V LVCMOS compatible
Non-inverted data output clock; 3V/5V LVCMOS compatible
Inverted data output clock; 3V/5V LVCMOS compatible
Non-inverted clock input pin; 100k pulldown to AGND, internally
Inverted clock input pin; 17.5k pullup to V
RESET synchronizes the data sampling and data output bank relationship when in dual channel
mode (DMODE
Inverted RESET input pin; 17.5k pullup to V
Internally: 100k pulldown to AGND on DMODE
Data output mode pins: DMODE
DMODE
DMODE
Power-Down pin; PD = 1 for Power-Down mode. Outputs set to high impedance in Power-Down
mode; 100k pulldown to AGND, internally
2.5V common mode voltage reference output
+5V analog supply
+3V/+5V digital output supply
Analog ground
Digital ground
1
1
= 0, DMODE
= 1, DMODE
1
= 0); 100k pulldown to AGND, internally
2
2
= 1: interleaved dual channel output
= x: single channel data output on bank a (125 MSPS max)
1
= 0, DMODE
pp
; 100k pullup to V
pp
; 100k pullup to V
cc
cc
and 7.5k pulldown to AGND, internally
and 7.5 pulldown to AGND, internally
1
2
50k pullup to V
= 0: parallel dual channel output
cc
and 100k pulldown to AGND, internally
cc
and 100k pulldown to AGND, internally
cc
on DMODE
2
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2