CDK1307 Cadeka Microcircuits LLC., CDK1307 Datasheet
CDK1307
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CDK1307 Summary of contents
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... The CDK1307 has a highly linear THA optimized for frequencies up to Nyquist. The differential clock interface is optimized for low jitter clock sources and supports LVDS, LVPECL, sine wave, and CMOS clock inputs. ...
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... Data Sheet Pin Configuration QFN-40 DVDD 1 CM_EXT 2 AVDD 3 AVDD 4 CDK1307 QFN- AVDD 7 DVDDCLK 8 CLKP 9 CLKN 10 Pin Assignments Pin No. Pin Name Description 0 Ground connection for all power domains. Exposed pad VSS 1, 11, 16 DVDD Digital and I/O-ring pre driver supply voltage, 1.8V ...
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Data Sheet Pin Assignments (Continued) Pin No. Pin Name Description 23 D_4 Output Data 24 ORNG Out of Range flag. High when input signal is out of range 27 CLK_EXT Output clock signal for data synchronization. CMOS levels 28 D_5 ...
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Data Sheet Absolute Maximum Ratings The safety of the device is not guaranteed when it is operated above the “Absolute Maximum Ratings”. The device should not be operated at these “absolute” limits. Adhere to the “Recommended Operating Conditions” for proper ...
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Data Sheet Electrical Characteristics (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 20/40/65/80MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 13-bit output, unless otherwise noted) Symbol Parameter DC Accuracy No Missing Codes Offset Error ...
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... Data Sheet Electrical Characteristics - CDK1307A (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 20MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 13-bit output, unless otherwise noted) Symbol Parameter Performance SNR Signal to Noise Ratio SINAD Signal to Noise and Distortion Ratio SFDR Spurious Free Dynamic Range ...
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... Data Sheet Electrical Characteristics - CDK1307B (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 40MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 13-bit output, unless otherwise noted) Symbol Parameter Performance SNR Signal to Noise Ratio SINAD Signal to Noise and Distortion Ratio SFDR Spurious Free Dynamic Range ...
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... Data Sheet Electrical Characteristics - CDK1307C (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 65MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 13-bit output, unless otherwise noted) Symbol Parameter Performance SNR Signal to Noise Ratio SINAD Signal to Noise and Distortion Ratio SFDR Spurious Free Dynamic Range ...
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... Data Sheet Electrical Characteristics - CDK1307D (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 80MSPS clock, 50% clock duty cycle, -1dBFS 8MHz input signal, 13-bit output, unless otherwise noted) Symbol Parameter Performance SNR Signal to Noise Ratio SINAD Signal to Noise and Distortion Ratio SFDR Spurious Free Dynamic Range ...
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Data Sheet Digital and Timing Electrical Characteristics (AVDD = 1.8V, DVDD = 1.8V, DVDDCLK = 1.8V, OVDD = 2.5V, 20/40/65/80MSPS clock, 50% clock duty cycle, -1 dBFS input signal, 5pF capacitive load, unless otherwise noted) Symbol Parameter Clock Inputs Duty ...
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... Data Sheet CLK_EXT Recommended Usage Analog Input The analog inputs to the CDK1307 is a switched capacitor track-and-hold amplifier optimized for differential opera- tion. Operation at common mode voltages at mid supply is recommended even if performance will be good for the ranges specified. The CM_EXT pin provides a voltage suit- able as common mode voltage reference ...
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... Figure 6. Alternative Input Network Clock Input And Jitter Considerations Typically high-speed ADCs use both clock edges to gener- ate internal timing signals. In the CDK1307 only the rising edge of the clock is used. Hence, input clock duty cycles between 20% and 80% is acceptable. The input clock can be supplied in a variety of formats. ...
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... OE_N signal high. ε is the total rms t The CDK1307 employs digital offset correction. This means that the output code will be 4096 with shorted inputs. However, small mismatches in parasitics at the input can cause this to alter slightly. The offset correction also re- sults in possible loss of codes at the edges of the full scale range ...
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Data Sheet Table 1: Data Format Description for 2V Differential Input Voltage (IP - IN) 1.0 V +0.24mV -0.24mV -1.0V Reference Voltages The reference voltages are internally generated and buff- ered based on a bandgap voltage reference. No external decoupling ...
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... CADEKA; nor does the purchase, lease, or use of a product or service from CADEKA convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual property rights of CADEKA or of third parties. Copyright ©2009 by CADEKA Microcircuits LLC. All rights reserved. Symbol ...