CDK8307 Cadeka Microcircuits LLC., CDK8307 Datasheet - Page 2

• Manufacturer Part Number: CDK8307
• Description: 12/13-bit, 20/40/50/65/80msps, Eight Channel, Ultra Low Power Adc With Lvds
• Manufacturer: Cadeka Microcircuits LLC.

PRELIMINARY Data Sheet
Table of Contents
Features .................................................................. 1
Applications ............................................................ 1
General Description ................................................ 1
Block Diagram ........................................................ 1
Table of Contents ................................................... 2
Ordering Information ............................................. 3
Pin Configurations .................................................. 4
Pin Assignments .................................................. 5-8
Absolute Maximum Ratings ................................... 9
Reliability Information ........................................... 9
ESD Protection ........................................................ 9
Recommended Operating Conditions .................... 9
Electrical Characteristics ...................................... 10
Electrical Characteristics – CDK8307A ................ 10
Electrical Characteristics – CDK8307B ................ 11
Electrical Characteristics – CDK8307C ................ 11
Electrical Characteristics – CDK8307D ................ 12
Electrical Characteristics – CDK8307E ................ 12
Digital and Timing Electrical Characteristics ...... 13
LVDS Timing Diagrams ......................................... 14
Serial Interface ..................................................... 15
Serial Register Map ..........................................16-17
Description of Serial Registers ........................17-24
©2009 CADEKA Microcircuits LLC
Figure 1. 12-bit Output, DDR Mode ......................... 14
Figure 2. 14-bit Output, DDR Mode ......................... 14
Figure 3. 12-bit Output, SDR Mode ......................... 14
Figure 4. Data Timing ............................................ 14
Timing Diagram .................................................... 15
Register Initialization ............................................. 15
Table 2. Summary of Functions Supported
Table 3. Software Reset ......................................... 17
Table 4. Power-Down Modes .................................. 17
Table 5. LVDS Drive Strength Programmability ......... 18
Figure 5. Serial Port Interface Timing Diagram ..... 15
Table 1. Serial Port Interface Timing Definitions ... 15
by Serial Interface ................................16-17
Theory of Operation ............................................. 26
Recommended Usage ........................................... 26
Mechanical Dimensions ...................................29-30
Table 6. LVDS Output Drive Strength for
Table 7. LVDS Internal Termination
Table 8. Bit Clock Internal Termination .................... 19
Table 9. Analog Input Invert ................................... 19
Table 10. LVDS Test Patterns .................................. 20
Table 11. Programmable Gain ................................. 20
Table 12. Gain Setting for Channels 1-8 .................. 21
Table 13. LVDS Clock Programmability and
Figure 6. Phase Programmability Modes for LCLK ..... 22
Figure 7. SDR Interface Modes ............................... 22
Table 14. Number of Serial Output Bits ................... 22
Figure 8. LVDS Output Timing Adjustment .............. 23
Table 16. Register Values with Corresponding
Table 17. Clock Frequency ...................................... 24
Table 18. Clock Frequency Settings ......................... 24
Table 19. Performance Control................................ 24
Table 20. Performance Control Settings ................... 25
Table 21. External Common Mode Voltage
Analog Input ......................................................... 26
DC-Coupling .......................................................... 26
AC-Coupling .......................................................... 27
Clock Input and Jitter Considerations ...................... 28
QFN-64 Package.................................................... 29
TQFP-80 Package .................................................. 30
Table 15. Full Scale Control .................................... 23
Figure 9. Input Configuration Diagram ................ 26
Figure 10. DC-Coupled Input .............................. 26
Figure 11. Transformer Coupled Input ................. 27
Figure 12. AC-Coupled Input .............................. 27
Figure 13. Alternative Input Network ................... 27
LCLK, FCLK, and Data ............................... 18
Programmability ....................................... 19
Data Output Modes ................................. 21
Charge in Full-Scale Range ...................... 24
Buffer Driving Strength ........................... 25
www.cadeka.com
2