CDK8307 Cadeka Microcircuits LLC., CDK8307 Datasheet - Page 22

• Manufacturer Part Number: CDK8307
• Description: 12/13-bit, 20/40/50/65/80msps, Eight Channel, Ultra Low Power Adc With Lvds
• Manufacturer: Cadeka Microcircuits LLC.

PRELIMINARY Data Sheet
The device can also be made to operate in SDR mode by setting the en_sdr bit to '1'. The bit clock (LCLK) is output at
12x times the input clock in this mode, two times the rate in DDR mode. Depending on the state of fall_sdr, LCLK may
be output in either of the two manners shown in Figure 7. As can be seen in Figure 7, only the LCLK rising (or falling)
edge is used to capture the output data in SDR mode. The SDR mode is not recommended beyond 40MSPS because the
LCLK frequency becomes very high.
The default data output format is offset binary. Two's complement mode can be selected by setting the btc_mode bit to
'1' which inverts the MSB.
The first bit of the frame (following the rising edge of FCLKP) is the LSB of the ADC output for default settings. Program-
ming the msb_first mode results in reverse bit order, and the MSB is output as the first bit following the FCLKP rising edge.
Table 14. Number of Serial Output Bits
©2009 CADEKA Microcircuits LLC
lvds_num_bits
lvds_advance
lvds_delay
Name
Sets the number if LVDS output bits 12-bit
Advance LVDS data bits and frame
clock by one clock cycle
Delay LVDS data bits and frame
clock by one clock cycle
PHASE_DDR<1:0>=’10’ = 90° (Default)
Dxx<1:0>
Dxx<1:0>
Dxx<1:0>
FCLKN
FCLKP
LCLKN
FCLKN
FCLKN
LCLKP
FCLKP
LCLKP
LCLKN
FCLKP
LCLKN
LCLKP
PHASE_DDR<1:0>=’00’ = 270°
Description
EN_SDR=’1’, FALL_SDR_’0’
Figure 6. Phase Programmability Modes for LCLK
Figure 7. SDR Interface Modes
Inactive
Inactive
Default
Dxx<1:0>
Dxx<1:0>
Dxx<1:0>
FCLKN
FCLKN
FCLKN
FCLKP
LCLKN
FCLKP
LCLKN
FCLKP
LCLKN
LCLKP
LCLKP
LCLKP
5
PHASE_DDR<1:0>=’01’ =180°
D
1
PHASE_DDR<1:0>=’11’ = 0°
D
1
4
EN_SDR=’1’, FALL_SDR_’1’
D
3
1
D
1
2
D
1
1
D
0
1
D
9
D
8
D
7
D
6
D
X
5
0
D
4
X
0
D
3
D
2
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D
1
X
D
0
Address
In Hex
53
22