ADT7476 Analog Devices, Inc., ADT7476 Datasheet - Page 29

• Manufacturer Part Number: ADT7476
• Description: Dbcool Remote Thermal Controller And Voltage Monitor
• Manufacturer: Analog Devices, Inc.

When using the THERM timer, be aware of the following.
After a THERM timer read (Register 0x79):
1.
2.
If the THERM timer is read during a THERM assertion, the
following happens:
1.
The contents of the timer are cleared on read.
The F4P bit (Bit 5) of Status Register 2 needs to be cleared
(assuming that the THERM timer limit has been
exceeded).
The contents of the timer are cleared.
(REG. 0x79)
(REG. 0x79)
(REG. 0x79)
THERM
THERM
THERM
THERM
THERM
THERM
TIMER
TIMER
TIMER
ACCUMULATE THERM LOW
ACCUMULATE THERM LOW
Figure 32. Understanding the THERM Timer
ASSERTION TIMES
ASSERTION TIMES
0 0 0
7 6 5
0 0 0
7 6 5
0 0 0
7 6 5
(REGISTER 0x7A)
THERM LIMIT
0
4
0
4
0
4
0 0 0 1
3 2 1 0
0 0 1 0
3 2 1 0
0 1 0 1
3 2 1 0
THERM ASSERTED ≥ 113.8ms
728.32ms
364.16ms
182.08ms
91.04ms
45.52ms
22.76ms
2.914s
1.457s
(91.04ms + 22.76ms)
THERM ASSERTED
THERM ASSERTED
≤ 22.76ms
≥ 45.52ms
Figure 33. Functional Block Diagram of THERM Monitoring Circuitry
0
1
2
3
4
5
6
COMPARATOR
7
Rev. B | Page 29 of 72
CLEARED
ON READ
7 6 5 4 3 2 1 0
IN
2.
3.
Generating SMBALERT Interrupts from THERM Timer
Events
The ADT7476 can generate an SMBALERT when a
programmable THERM timer limit is exceeded. This allows the
system designer to ignore brief, infrequent THERM assertions
while capturing longer THERM timer events. Register 0x7A is
the THERM timer limit register. This 8-bit register allows a
limit from 0 seconds (first THERM assertion) to 5.825 seconds
to be set before an SMBALERT is generated. The THERM timer
value is compared with the contents of the THERM timer limit
register. If the THERM timer value exceeds the THERM timer
limit value, then the F4P bit (Bit 5) of Interrupt Status Register 2
(0x42) is set and an SMBALERT is generated.
Note that, depending on which pins are configured as a THERM
timer, setting the F4P bit (Bit 5) of Interrupt Mask Register 2
(0x75) or Bit 0 of Interrupt Mask Register 1 (0x74) masks out
SMBALERT , although the F4P bit of Interrupt Status Register 2 is
still set if the THERM timer limit is exceeded.
Figure 33 is a functional block diagram of the THERM timer,
limit, and associated circuitry. Writing a value of 0x00 to the
THERM timer limit register (0x7A) causes an SMBALERT to be
generated on the first THERM assertion. A THERM timer limit
value of 0x01 generates an SMBALERT once cumulative
THERM assertions exceed 45.52 ms.
LATCH
RESET
OUT
Bit 0 of the THERM timer is set to 1 because a THERM
assertion is occurring. The THERM timer increments
from zero.
If the THERM timer limit (Reg. 0x7A) = 0x00, the F4P bit
is set.
1 = MASK
MASK REGISTER 2
STATUS REGISTER 2
(REGISTER 0x75)
F4P BIT (BIT 5)
F4P BIT (BIT 5)
THERM TIMER CLEARED ON READ
2.914s
1.457s
728.32ms
364.16ms
182.08ms
91.04ms
45.52ms
22.76ms
(REGISTER 0x79)
THERM TIMER
SMBALERT
THERM
ADT7476