HY27US0812B Hynix Semiconductor, HY27US0812B Datasheet - Page 13

• Manufacturer Part Number: HY27US0812B
• Description: 512mb Nand Flash
• Manufacturer: Hynix Semiconductor

3.3 Block Erase.
The Erase operation is done on a block (16K Byte) basis. It consists of an Erase Setup command (60h), a Block
address loading and an Erase Confirm Command (D0h). The Erase Confirm command (D0h) following the block
address loading initiates the internal erasing process. This two-step sequence of setup followed by execution com-
mand ensures that memory contents are not accidentally erased due to external noise conditions.
The block address loading is accomplished three cycles. Only block addresses (A14 to A25 , highest address depending
on the device density) are needed while A9 to A13 is ignored.
At the rising edge of WE after the erase confirm command input, the internal Program Erase Controller handles erase
and erase-verify. When the erase operation is completed, the Write Status Bit (I/O 0) may be checked. Figure 17
details the sequence.
3.4 Copy-Back Program.
The copy-back program is provided to quickly and efficiently rewrite data stored in one page within the plane to
another page within the same plane without using an external memory. Since the time-consuming sequential reading
and its reloading cycles are removed, the system performance is improved. The benefit is especially
obvious when a portion of a block is updated and the rest of the block also need to be copied to the newly assigned
free block. The operation for performing a copy-back program is a sequential execution of page-read without burst-
reading cycle and copying-program with the address of destination page. A normal read operation with "00h" com-
mand and the address of the source page moves the whole 528byte data into the internal buffer.
As soon as the device returns to Ready state, Page-Copy Data-input command (8Ah) with the address cycles of desti-
nation page followed may be written. The Program Confirm command (10h) is not needed to actually begin the pro-
gramming operation. For backward-compatibility, issuing Program Confirm command during copy-back does not affect
correct device operation.
Copy-Back Program operation is allowed only within the same memory plane. Once the Copy-Back Program is finished,
any additional partial page programming into the copied pages is prohibited before erase. Plane address must be the
same between source and target page.
"When there is a program-failure at Copy-Back operation, error is reported by pass/fail status. But, if Copy-Back oper-
ations are accumulated over time, bit error due to charge loss is not checked by external error detection/correction
scheme. For this reason, two bit error correction is recommended for the use of Copy-Back operation."
Figure 16 shows the command sequence for the copy-back operation.
The Copy Back Program operation requires three steps:
1. The source page must be read using the Read A command (one bus write cycle to setup the command and then
2. When the device returns to the ready state (Ready/Busy High), the second bus write cycle of the command is
3. Then the confirm command is issued to start the P/E/R Controller.
Rev 0.5 / Jul. 2007
given with the 4bus cycles to input the target page address. The value for A25 from second to the last page address
4 bus write cycles to input the source page address). This operation copies all 2KBytes from the page into the Page
Buffer.
must be same as the value given to A25 in first address.
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
HY27US(08/16)12(1/2)B Series
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