MPC8260 Freescale Semiconductor, Inc, MPC8260 Datasheet
MPC8260
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MPC8260 Summary of contents
Page 1
... DC/AC electrical characteristics, and AC timing specifications for .25µm (HiP4) devices in the PowerQUICC II™ MPC8260 communications processor family. These devices include the MPC8260, the MPC8255, the MPC8264, the MPC8265, and the MPC8266. Throughout this document, these devices are collectively referred to as the MPC826xA. ...
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... System core microprocessor supporting frequencies of 150–300 MHz — Separate 16-Kbyte data and instruction caches: – Four-way set associative – Physically addressed – LRU replacement algorithm MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1 Kbytes I-Cache I-MMU 16 Kbytes ...
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... IEEE 1149.1 JTAG test access port • Twelve-bank memory controller — Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash and other user- definable peripherals — Byte write enables and selectable parity generation MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1 Freescale Semiconductor Features 3 ...
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... Binary synchronous (BISYNC) communications – Transparent — Two serial management controllers (SMCs), identical to those of the MPC860 – Provide management for BRI devices as general circuit interface (GCI) controllers in time- division-multiplexed (TDM) channels MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1 4 Freescale Semiconductor ...
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... Cell delineation using bit by bit HEC checking and programmable ALPHA and DELTA parameters for the delineation state machine - Payload descrambling using self synchronizing scrambler (programmable by the user) MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1 Freescale Semiconductor 2 C) controller (identical to the MPC860 I ...
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... Includes all of the configuration registers (which are automatically loaded from the EPROM and used to configure the MPC8265) required by the PCI standard as well as message and doorbell registers — Supports the I O standard 2 MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1 capabilities Freescale Semiconductor ...
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... Caution: VDDH can exceed VDD/VCCSYN by 3.3 V during power on reset by no more than 100 mSec. VDDH should not exceed VDD/VCCSYN by more than 2.5 V during normal operation. 4. Caution: VIN must not exceed VDDH by more than 2 any time, including during power-on reset. MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1 Freescale Semiconductor Table 1. Absolute Maximum Ratings ...
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... MPC8280. Note that in PCI mode the I/O interface is different GND – 0 GND – 1.0 V MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1 8 Symbol (2) VDD 1.7 – 1.9 2 VCCSYN 1.7 – 1.9 VDDH 3.135 – ...
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... Output high voltage – except XFC, UTOPIA mode, and open drain pins In UTOPIA mode -8.0mA OH PA[0-31] PB[4-31] PC[0-31] PD[4-31] In UTOPIA mode 8.0mA OL PA[0-31] PB[4-31] PC[0-31] PD[4-31] MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1 Freescale Semiconductor Table 3. DC Electrical Characteristics Symbol IHC V ILC ( VDDH I ...
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... DP(3)/IRQ3/EXT_BR3/CKSTP_OUT DP(4)/IRQ4/EXT_BG3/CORE_SREST DP(5)/TBEN/IRQ5/EXT_DBG3 DP(6)/CSE(0)/IRQ6 DP(7)/CSE(1)/IRQ7 PSDVAL TA TEA GBL/IRQ1 CI/BADDR29/IRQ2 WT/BADDR30/IRQ3 L2_HIT/IRQ4 CPU_BG/BADDR31/IRQ5 CPU_DBG CPU_BR IRQ0/NMI_OUT IRQ7/INT_OUT/APE PORESET HRESET SRESET RSTCONF QREQ MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1 10 (1) (continued) Symbol Min Max V — 0.4 OL Freescale Semiconductor Unit V ...
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... L_A27/GNT2 /HSENUM 3 L_A28/RST /CORE_SRESET 3 L_A29/INTA 3 L_A30/REQ2 L_A31 3 LCL_D(0-31)/AD(0-31) 3 LCL_DP(0-3)/C/BE(0-3) PA[0–31] PB[4–31] PC[0–31] PD[4–31] TDO MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1 Freescale Semiconductor Symbol Electrical and Thermal Characteristics (1) (continued) Min Max Unit — 0 ...
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... Watts (chip internal power) INT power dissipation on input and output pins (determined by user) I/O < 0 For most applications P I the following: J MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1 12 Symbol Value ( θ θ θ ...
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... Multiplier 66.66 2 66.66 2.5 66.66 3 66.66 3 4.5 83.33 2 83.33 2 83.33 2.5 3.5 MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1 Freescale Semiconductor θ Using this value of K the values power supply should be bypassed to ground using at least four CC and ground should be kept to less than half an CC and GND circuits ...
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... TIMER/IDMA outputs sp42a sp43a PIO outputs Notes: 1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are measured at the pin. MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1 14 ° C) Table 6. Table 6. Output Buffer Impedances Typical Impedance (Ω ...
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... FCC external clock. Serial ClKin FCC input signals FCC output signals Note: When GFMR[TCI FCC output signals Note: When GFMR[TCI MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1 Freescale Semiconductor Characteristic sp17b sp16b sp36b/sp37b Figure 3. FCC External Clock Diagram ...
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... Input sampled on the rising edge and output driven on the falling edge. 3. Input sampled on the falling edge and output driven on the falling edge. 4. Input sampled on the falling edge and output driven on the rising edge. Figure 5. SCC/SMC/SPI/I MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1 16 sp17a sp36a/sp37a Figure 4 ...
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... Input sampled on the rising edge and output driven on the falling edge. 3. Input sampled on the falling edge and output driven on the falling edge. 4. Input sampled on the falling edge and output driven on the rising edge. MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1 Freescale Semiconductor 2 C internal clock ...
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... All other pins Notes: 1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are measured at the pin. MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1 18 Sys clk sp22 (See note) (See note) output signals Table 9 ...
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... AC timing. When data pipelining is activated, sp12 can be used for data bus setup even when ECC or PARITY are used. Also, sp33a can be used as the AC specification for DP signals. MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1 Freescale Semiconductor Max Delay (ns) ...
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... DATA bus output signals All other output signals Figure 10 shows signal behavior for all parity modes (including ECC, RMW parity, and standard parity). DATA bus, ECC, and PARITY mode input signals MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1 20 sp11 sp12 sp15 ...
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... Figure graphical representation of CLKin T1 CLKin T1 CLKin T1 Figure 12. Internal Tick Spacing for Memory Controller Signals MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1 Freescale Semiconductor sp34/sp30 Figure 11. MEMC Mode Diagram NOTE Tick Spacing (T1 Occurs at the Rising Edge of CLKin 1/4 CLKin ...
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... The UPM machine outputs change on the internal tick determined by the memory controller programming; the AC specifications are relative to the internal tick. Note that SDRAM and GPCM machine outputs change on CLKin’s rising edge. MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1 22 Table 12. JTAG Timings 2 ...
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... Input Clock MODCK_H–MODCK[1–3] Frequency 0001_000 33 MHz 0001_001 33 MHz 0001_010 33 MHz 0001_011 33 MHz 0001_100 33 MHz MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1 Freescale Semiconductor Table 13 NOTE Table 13. Clock Default Modes CPM Multiplication CPM Factor Frequency 3 100 MHz 3 100 MHz ...
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... MHz 0011_100 33 MHz 0011_101 33 MHz 0011_110 33 MHz 0011_111 33 MHz 0100_000 33 MHz 0100_001 0100_010 0100_011 0100_100 0100_101 0100_110 MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1 24 CPM Multiplication CPM (2) 2 Factor Frequency ,(3) 3 100 MHz 3 100 MHz 3 100 MHz 3 100 MHz ...
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... MHz 0111_001 66 MHz 0111_010 66 MHz 0111_011 66 MHz 0111_100 66 MHz 0111_101 66 MHz 0111_110 66 MHz 0111_111 66 MHz 1000_000 66 MHz MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1 Freescale Semiconductor CPM Multiplication CPM (2) 2 Factor Frequency ,(3) Reserved 2 133 MHz 2 133 MHz 2 133 MHz 2 ...
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... The minimum Tval = 2 when PCI_MODCK = 1, and the minimum Tval = 1 when PCI_MODCK = 0. Therefore, designers should use clock configurations that fit this condition to achieve PCI-compliant AC timing. Clock configurations change only after POR is asserted. MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1 26 CPM Multiplication CPM ...
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... MHz 0010_001 33 MHz 0010_010 33 MHz 0010_011 33 MHz (3) 0011_000 33 MHz 3 0011_001 33 MHz MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1 Freescale Semiconductor and Table 17 are for the purpose of illustration only. Users must select CPM Core CPM Multiplication Frequency Factor Factor 2 133 MHz 2 ...
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... MHz 0111_011 66 MHz 0111_100 66 MHz 1000_000 66 MHz 1000_001 66 MHz 1000_010 66 MHz 1000_011 66 MHz 1000_100 66 MHz 1001_000 66 MHz MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1 28 CPM Core CPM Multiplication Frequency Factor Factor 5 166 MHz 7 5 166 MHz 8 6 200 MHz ...
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... Table 18. Clock Default Configurations in PCI Agent Mode (MODCK_HI = 0000) Input Clock MODCK[1–3] Frequency Multiplication (1) 2 (PCI) 000 66/33 MHz 001 66/33 MHz 010 66/33 MHz 011 66/33 MHz MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1 Freescale Semiconductor CPM Core CPM Multiplication Frequency Factor Factor 3.5 233 MHz 3 3.5 233 MHz 3.5 3.5 ...
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... MHz 0010_100 50/25 MHz 0011_000 66/33 MHz 0011_001 66/33 MHz 0011_010 66/33 MHz 0011_011 66/33 MHz 0011_100 66/33 MHz 0100_000 66/33 MHz 0100_001 66/33 MHz 0100_010 66/33 MHz MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1 30 CPM Core CPM Multiplication Frequency (2) Factor Factor 3/6 200 MHz 3 3/6 200 MHz 3.5 4/8 266 MHz 3.5 ...
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... MHz 1000_011 66/33 MHz 1000_100 66/33 MHz 1000_101 66/33 MHz 1001_000 66/33 MHz 1001_001 66/33 MHz 1001_010 66/33 MHz 1001_011 66/33 MHz 1001_100 66/33 MHz MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1 Freescale Semiconductor CPM Core CPM Multiplication Frequency 1 Factor Factor 3/6 200 MHz 4 3/6 200 MHz 4.5 5 166 MHz 2 ...
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... Core frequency = (60x bus frequency)(core multiplication factor) 4. Bus frequency = CPM frequency / bus division factor 5. In this mode, PCI_MODCK must be “1”. MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1 32 CPM Core ...
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... Not to Scale Figure 13. Pinout of the 480 TBGA Package as Viewed from the Top Surface MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1 Freescale Semiconductor ...
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... A10 A11 A12 A13 A14 A15 A16 A17 MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1 34 View Die Attach Die Glob-Top Filled Area Glob-Top Dam Wire Bonds Figure 14. Side View of the TBGA Package Table 21 defines conventions and acronyms used in Table 20 ...
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... TT1 TT2 TT3 TT4 TBST TSIZ0 TSIZ1 TSIZ2 TSIZ3 AACK ARTRY DBG DBB/IRQ3 MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1 Freescale Semiconductor Table 20. Pinout List (continued) Pin Name Ball ...
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... D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40 D41 MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1 36 Table 20. Pinout List (continued) Pin Name Ball B5 A20 E17 B15 B13 A11 D19 D17 D15 ...
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... D62 D63 DP0/RSRV/EXT_BR2 IRQ1/DP1/EXT_BG2 IRQ2/DP2/TLBISYNC/EXT_DBG2 IRQ3/DP3/CKSTP_OUT/EXT_BR3 IRQ4/DP4/CORE_SRESET/EXT_BG3 IRQ5/DP5/TBEN/EXT_DBG3 IRQ6/DP6/CSE0 IRQ7/DP7/CSE1 PSDVAL TA TEA GBL/IRQ1 CI/BADDR29/IRQ2 MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1 Freescale Semiconductor Table 20. Pinout List (continued) Pin Name Ball A14 B12 A10 C18 E16 B14 C12 B10 ...
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... ALE BCTL0 PWE0/PSDDQM0/PBS0 PWE1/PSDDQM1/PBS1 PWE2/PSDDQM2/PBS2 PWE3/PSDDQM3/PBS3 PWE4/PSDDQM4/PBS4 PWE5/PSDDQM5/PBS5 PWE6/PSDDQM6/PBS6 PWE7/PSDDQM7/PBS7 PSDA10/PGPL0 PSDWE/PGPL1 POE/PSDRAS/PGPL2 PSDCAS/PGPL3 PGTA/PUPMWAIT/PGPL4/PPBS PSDAMUX/PGPL5 MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1 38 Table 20. Pinout List (continued) Pin Name Ball F25 C29 E27 E28 F26 F27 F28 ...
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... L_A28/RST /CORE_SRESET 1 L_A29/INTA 1 L_A30/REQ2 1 L_A31/DLLOUT 1 LCL_D0/AD0 1 LCL_D1/AD1 1 LCL_D2/AD2 1 LCL_D3/AD3 1 LCL_D4/AD4 1 LCL_D5/AD5 MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1 Freescale Semiconductor Table 20. Pinout List (continued) Pin Name ( Ball H28 H27 H26 G29 D27 C28 E26 D25 C26 ...
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... LCL_DP1/C1 /BE1 1 1 LCL_DP2/C2 /BE2 1 1 LCL_DP3/C3 /BE3 IRQ0/NMI_OUT IRQ7/INT_OUT/APE TRST TCK TMS MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1 40 Table 20. Pinout List (continued) Pin Name Ball K25 L29 L27 L26 L25 M29 M28 M27 M26 N29 T25 U27 ...
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... PA8/SMRXD2/L1RXD0A1/L1RXDA1 PA9/SMTXD2/L1TXD0A1 PA10/FCC1_UT8_RXD0/FCC1_UT16_RXD8/MSNUM5 PA11/FCC1_UT8_RXD1/FCC1_UT16_RXD9/MSNUM4 PA12/FCC1_UT8_RXD2/FCC1_UT16_RXD10/MSNUM3 PA13/FCC1_UT8_RXD3/FCC1_UT16_RXD11/MSNUM2 PA14/FCC1_UT8_RXD4/FCC1_UT16_RXD12/FCC1_RXD3 PA15/FCC1_UT8_RXD5/FCC1_UT16_RXD13/FCC1_RXD2 PA16/FCC1_UT8_RXD6/FCC1_UT16_RXD14/FCC1_RXD1 PA17/FCC1_UT8_RXD7/FCC1_UT16_RXD15/FCC1_RXD0/FCC1_RXD PA18/FCC1_UT8_TXD7/FCC1_UT16_TXD15/FCC1_TXD0/FCC1_TXD PA19/FCC1_UT8_TXD6/FCC1_UT16_TXD14/FCC1_TXD1 PA20/FCC1_UT8_TXD5/FCC1_UT16_TXD13/FCC1_TXD2 PA21/FCC1_UT8_TXD4/FCC1_UT16_TXD12/FCC1_TXD3 MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1 Freescale Semiconductor Table 20. Pinout List (continued) Pin Name Ball AE6 AF5 AB4 AG6 AH5 AF6 AA3 AJ4 W2 W3 ...
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... PB10/FCC2_UT8_TXD1/FCC3_RXD2/L1RXDD1 PB11/FCC3_RXD3/FCC2_UT8_TXD0/L1TXDD1 PB12/FCC3_MII_CRS/L1CLKOB1/L1RSYNCC1/TXD2 PB13/FCC3_MII_COL/L1RQB1/L1TSYNCC1/L1GNTC1/L1TXD1A2 PB14/FCC3_MII_TX_EN/RXD3/L1RXDC1 PB15/FCC3_MII_TX_ER/RXD2/L1TXDC1 PB16/FCC3_MII_RX_ER/L1CLKOA1/CLK18 PB17/FCC3_MII_RX_DV/L1RQA1/CLK17 PB18/FCC2_UT8_RXD4/FCC2_RXD3/L1CLKOD2/L1RXD2A2 PB19/FCC2_UT8_RXD5/FCC2_RXD2/L1RQD2/L1RXD3A2 PB20/FCC2_UT8_RXD6/FCC2_RXD1/L1RSYNCD2/L1TXD1A1 PB21/FCC2_UT8_RXD7/FCC2_RXD0/FCC2_RXD/L1TSYNCD2/L1GNTD2/ L1TXD2A1 PB22/FCC2_UT8_TXD7/FCC2_TXD0/FCC2_TXD/L1RXD1A1/L1RXDD2 PB23/FCC2_UT8_TXD6/FCC2_TXD1/L1RXD2A1/L1TXDD2 PB24/FCC2_UT8_TXD5/FCC2_TXD2/L1RXD3A1/L1RSYNCC2 PB25/FCC2_UT8_TXD4/FCC2_TXD3/L1TSYNCC2/L1GNTC2/L1TXD3A1 PB26/FCC2_MII_CRS/FCC2_UT8_TXD1/L1RXDC2 MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1 42 Table 20. Pinout List (continued) Pin Name Ball 2 AF12 2 AG11 2 AH9 2 AJ8 2 AH7 2 AF7 2 AD5 ...
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... PC12/CD2/RENA2/SI1_L1ST3/FCC1_UTM_RXADDR1/ FCC1_UTS_RXADDR1 PC13/CTS2/CLSN2/L1RQD1/FCC1_UTM_TXADDR1/ FCC1_UTS_TXADDR1 PC14/CD1/RENA1/FCC1_UTM_RXADDR0/FCC1_UTS_RXADDR0 PC15/CTS1/CLSN1/SMTXD2/FCC1_UTM_TXADDR0/ FCC1_UTS_TXADDR0 PC16/CLK16/TIN4 PC17/CLK15/TIN3/BRGO8 PC18/CLK14/TGATE2 PC19/CLK13/BRGO7/SPICLK PC20/CLK12/TGATE1 PC21/CLK11/BRGO6 PC22/CLK10/DONE1 PC23/CLK9/BRGO5/DACK1 PC24/FCC2_UT8_TXD3/CLK8/TOUT4 PC25/FCC2_UT8_TXD2/CLK7/BRGO4 MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1 Freescale Semiconductor Table 20. Pinout List (continued) Pin Name Ball 2 AH6 2 AE3 2 AE2 2 AC5 2 AC4 2 AB26 ...
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... PD15/FCC1_UT16_RXD1/L1RQC2/I2CSDA PD16/FCC1_UT_TXPRTY/L1TSYNCC1/L1GNTC1/SPIMISO PD17/FCC1_UT_RXPRTY/BRGO2/SPIMOSI PD18/FCC1_UTM_RXADDR4/FCC1_UTS_RXADDR4/ FCC1_UTM_RXCLAV3/FCC2_UTM_RXADDR3/SPICLK PD19/FCC1_UTM_TXADDR4/FCC1_UTS_TXADDR4/ FCC1_UTM_TXCLAV3/FCC2_UTM_TXADDR3/SPISEL/BRGO1 PD20/RTS4/TENA4/FCC1_UT16_RXD2/L1RSYNCA2 PD21/TXD4/FCC1_UT16_RXD3/L1RXD0A2/L1RXDA2 PD22/RXD4/FCC1_UT16_TXD5/L1TXD0A2/L1TXDA2 PD23/RTS3/TENA3/FCC1_UT16_RXD4/L1RSYNCD1 PD24/TXD3/FCC1_UT16_RXD5/L1RXDD1 PD25/RXD3/FCC1_UT16_TXD6/L1TXDD1 PD26/RTS2/TENA2/FCC1_UT16_RXD6/L1RSYNCC1 PD27/TXD2/FCC1_UT16_RXD7/L1RXDC1 PD28/RXD2/FCC1_UT16_TXD7/L1TXDC1 PD29/RTS1/TENA1/FCC1_UTM_RXADDR3/FCC1_UTS_RXADDR3/ FCC1_UTM_RXCLAV2/FCC2_UTM_RXADDR4 MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1 44 Table 20. Pinout List (continued) Pin Name Ball 2 AJ6 2 AG2 2 AF3 2 AF2 2 AE1 2 AD1 2 AC28 ...
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... Must be pulled down or left floating PCI devices (MPC8265 and MPC8266) this pin should be asserted if the PCI function is desired or pulled up or left floating if PCI is not desired. On non-PCI devices (MPC8260A and MPC8264) this is a spare pin that must be pulled up or left floating. ...
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... Package Parameters Package parameters are provided in Package Outline Interconnects Pitch Nominal unmounted package height 1.55 mm MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1 46 Table 21. Table 21. Symbol Legend Signals with overbars, such as TA, are active low. Indicates that a signal is part of the UTOPIA master interface. ...
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... Mechanical Dimensions Figure 15 provides the mechanical dimensions and bottom surface nomenclature of the 480 TBGA package. Figure 15. Mechanical Dimensions and Bottom Surface Nomenclature MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1 Freescale Semiconductor Package Description Notes: 1. Dimensions and Tolerancing per ASME Y14.5M-1994. ...
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... Change to sp20/sp21. 0.2 11/2001 • Revision of • Modifications to • Modification to pinout diagram, • Additional revisions to text and figures throughout MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1 XXX Figure 16. Freescale Part Number Key Table 23. Document Revision History Substantive Changes Table 5, “ ...
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... Note: In revision 0.3, sp30 in this “Document Revision History” Table. • Removal of “HiP4 PowerQUICC II Documentation” table. These supplemental specifications have been replaced by revision 1 of the MPC8260 PowerQUICC II™ Family Reference Manual . • Figure 1 • Addition of • Addition of VCCSYN to “Note: Core, PLL, and I/O Supply Voltages” following • ...
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... Document Revision History THIS PAGE INTENTIONALLY LEFT BLANK MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1 50 Freescale Semiconductor ...
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... THIS PAGE INTENTIONALLY LEFT BLANK MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1 Freescale Semiconductor Document Revision History 51 ...
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... Denver, Colorado 80217 1-800-441-2447 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor @hibbertgroup.com Document Number: MPC8260AEC Rev. 1.1 03/2006 Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. ...