PIC16F819 Microchip Technology Inc., PIC16F819 Datasheet - Page 80

• Manufacturer Part Number: PIC16F819
• Description: 18/20-pin Enhanced Flash Microcontrollers With Nanowatt Technology
• Manufacturer: Microchip Technology Inc.

PIC16F818/819
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF must be cleared in software and
the SSPSTAT register is used to determine the status
of the byte. Flag bit SSPIF is set on the falling edge of
the ninth clock pulse.
As a slave-transmitter, the ACK pulse from the master-
receiver is latched on the rising edge of the ninth SCL
input pulse. If the SDA line was high (not ACK), then
TABLE 10-2:
FIGURE 10-6:
FIGURE 10-7:
DS39598E-page 78
Note 1:
SDA
SCL
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
SSPOV (SSPCON<6>)
SDA
SCL
SSPIF (PIR1<3>)
BF (SSPSTAT<0>)
CKP (SSPCON<4>)
Transfer is Received
Status Bits as Data
BF
0
1
1
0
S
S
Shaded cells show the conditions where the user software did not properly clear the overflow condition.
A7 A6 A5 A4 A3 A2 A1
1
SSPOV
2
A7
Receiving Address
Data is
Sampled
DATA TRANSFER RECEIVED BYTE ACTIONS
1
0
0
1
1
3
A6
2
I
I
2
4
2
C™ WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
C™ WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
A5
Receiving Address
5
3
SSPSR
6
A4
4
R/W = 0
7
A3
5
Yes
8
No
No
No
A2
6
ACK
SSPBUF
9
A1
D7
1
7
D6
2
R/W = 1
SSPBUF register is read
8
Receiving Data
D5
3
Cleared in software
9
Generate ACK Pulse
D4
ACK
Bit SSPOV is set because the SSPBUF register is still full
4
responds to SSPIF
SCL held low
while CPU
D3
5
D2
6
Yes
the data transfer is complete. When the ACK is latched
by the slave device, the slave logic is reset (resets
SSPSTAT register) and the slave device then monitors
for another occurrence of the Start bit. If the SDA line
was low (ACK), the transmit data must be loaded into
the SSPBUF register which also loads the SSPSR
register. Then pin RB4/SCK/SCL should be enabled by
setting bit, CKP.
No
No
No
D1
7
D0
8
D7
SSPBUF is written in software
1
ACK
9
D6
2
Cleared in software
D7
Set bit after writing to SSPBUF
(the SSPBUF must be written to
before the CKP bit can be set)
1
D5
3
D6
2
(SSP interrupt occurs if enabled)
D4
D5
4
Receiving Data
3
D4
Transmitting Data
4
D3
5
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ACK is not sent
D3
5
D2
Set bit SSPIF
6
D2
6
From SSP Interrupt
Service Routine
D1
7
Yes
Yes
Yes
Yes
D1
7
D0
D0
8
8
ACK
9
ACK
9
transfer
Bus master
terminates
P
P