S25FL128R Meet Spansion Inc., S25FL128R Datasheet
S25FL128R
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S25FL128R Summary of contents
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... Notice to Readers: This document states the current technical specifications regarding the Spansion product(s) described herein. Each product described herein may be designated as Advance Information, Preliminary, or Full Production. See Publication Number S25FL128R_00 Notice On Data Sheet Designations Revision 02 Issue Date December 1, 2009 S25FL128R Cover Sheet for definitions. ...
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... Questions regarding these document designations may be directed to your local sales office range. Changes may also include those needed to clarify a IO S25FL128R S25FL128R_00_02 December 1, 2009 ...
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... General Description The S25FL128R is a 3.0 Volt (2.7V to 3.6V), single-power-supply Flash memory device. The device consists of 64 sectors of 256 KB memory, or 256 sectors memory. The S25FL128R device is fully backward compatible with the S25FL128P device. The device accepts data written to SI (Serial Input) and outputs data on SO (Serial Output). The devices are designed to be programmed in-system with the standard system 3 ...
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... SOC 008 wide — 8-pin Plastic Small Outline Package (208-mils Body Width 20.2 SO3 016 wide—16-pin Plastic Small Outline Package (300-mil Body Width 20.3 WSON 8-contact ( mm) No-Lead Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 21. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . S25FL128R S25FL128R_00_02 December 1, 2009 ...
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... Maximum Positive Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 18.1 AC Measurements I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 19.1 SPI Mode 0 (0,0) Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 19.2 SPI Mode 0 (0,0) Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Figure 19.3 HOLD# Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 19.4 Write Protect Setup and Hold Timing during WRSR when SRWD December 1, 2009 S25FL128R_00_02 ( S25FL128R 5 ...
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... S25FL128R Sector Address Table (Uniform 64 KB sector .17 Table 11.1 Manufacturer & Device Identification, RDID (9Fh .24 Table 11.2 READ_ID Command and Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Table 11.3 S25FL128R Status Register (Uniform 256 KB sector .28 Table 11.4 S25FL128R Status Register (Uniform 64 KB sector .28 Table 11.5 Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Table 11.6 Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Table 12.1 ACC Program Acceleration Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Table 13.1 Power-Up / Power-Down Voltage and Timing ...
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... Block Diagram SRAM Logic December 1, 2009 S25FL128R_00_02 ( Array - L RD DATA PATH IO S25FL128R X D Array - ...
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... PCB routing ensures 0 mV difference between voltage at the WSON SS Figure 2.3 8-pin Plastic Small Outline Package (SO) CS WP#/ACC GND S25FL128R SCK SI PO6 PO5 PO4 PO3 GND WP#/ACC VCC HOLD# SCK SI VCC HOLD# SCK SI S25FL128R_00_02 December 1, 2009 ...
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... WP#/ACC (Write Protect/Accelerated Programming GND 4. Logic Symbol December 1, 2009 S25FL128R_00_02 ( I/O Output Transfers data serially out of the device on the falling edge of SCK. Transfers parallel data into the device on the rising edge of SCK or out of Input/Output the device on the falling edge of SCK ...
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... SPEED 0X = DEVICE TECHNOLOGY R = DENSITY 128 = DEVICE FAMILY S25FL = Spansion Memory 3.0 Volt-only, Serial Peripheral Interface (SPI) Flash Memory Table 5.1 S25FL128R Valid Combinations Table S25FL128R Valid Combinations Speed Package & Model Option Temperature Number 00, 10 MFI 01 NFI S25FL128R ...
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... The Write Protect/Accelerated Programming (WP#/ACC) and Hold (HOLD#) signals should be driven high (logic level 1) or low (logic level 0) as appropriate. CPOL CPHA Mode Mode 3 December 1, 2009 S25FL128R_00_02 ( Figure 6.2 Figure 6.1 Bus Master and Memory Devices on the SPI Bus SO SI SCK SCK SO SI SCK SO SI ...
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... WP#/ACC input is driven low. In this mode, the non-volatile bits of the Status Register (SRWD, BP3, BP2, BP1, BP0) become read-only bits The Deep Power Down (DP) command provides additional data protection against 39): S25FL128R S25FL128R_00_02 December 1, 2009 ...
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... Disable (SRWD) bit together provide write protection. Clock Pulse Count: The device verifies that all program, erase, and Write Status Register commands consist of a clock pulse count that is a multiple of eight before executing them. Table 7.1 S25FL128R Protected Area Sizes (Uniform 256 KB sector) Status Register Block Protect Bits ...
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... Table 7.2 S25FL128R Protected Area Sizes (Uniform 64 KB sector) Status Register Block Protect Bits BP3 BP2 BP1 BP0 FE0000h-FFFFFFh FC0000h-FFFFFFh F80000h-FFFFFFh F00000h-FFFFFFh E00000h-FFFFFFh C00000h-FFFFFFh 800000h-FFFFFFh ...
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... KB sector) December 1, 2009 S25FL128R_00_02 ( Table 8.2 shows the starting and ending address for each Table 8.1 S25FL128R Device Organization Each Sector has Each Page has 262144 (256 KB sector) 65536 (64 KB sector) 1024 (256 KB sector) 256 (64 KB sector) — ...
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... Table 8.2 S25FL128R Sector Address Table (Uniform 256 KB sector) Sector Address Range Sector FC0000h FFFFFFh F80000h FBFFFFh F40000h ...
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... Table 8.3 S25FL128R Sector Address Table (Uniform 64 KB sector) (Sheet Sector Address Range 255 FF0000h FFFFFFh 254 FE0000h FEFFFFh 253 FD0000h FDFFFFh 252 FC0000h FCFFFFh 251 FB0000h FBFFFFh 250 FA0000h FAFFFFh 249 F90000h F9FFFFh 248 F80000h F8FFFFh ...
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... Table 8.3 S25FL128R Sector Address Table (Uniform 64 KB sector) (Sheet Sector Address Range 111 6F0000h 6FFFFFh 110 6E0000h 6EFFFFh 109 6D0000h 6DFFFFh 108 6C0000h 6CFFFFh 107 6B0000h 6BFFFFh 106 6A0000h 6AFFFFh 105 690000h 69FFFFh 104 680000h 68FFFFh 103 670000h 67FFFFh 102 ...
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... V for operations other than accelerated programming, or device damage may result. In addition, the WP#/ HH ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. December 1, 2009 S25FL128R_00_02 ( S25FL128R on this pin, the ...
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... Figure 11.1 Read Data Bytes (READ) Command Sequence Command 24-Bit Address MSB S25FL128R Data Out 1 Data Out MSB S25FL128R_00_02 December 1, 2009 ...
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... For parallel mode operation, the device requires an Enter Parallel Mode command (55h) before the READ command. An Exit Parallel Mode (45h) command or a power-down / power-up sequence is required to exit the parallel mode. December 1, 2009 S25FL128R_00_02 ( Figure 11 ...
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... presented at the SCK SCK and Table 11.6. The first byte specified can Dummy Byte MSB MSB DATA OUT 1 S25FL128R_00_02 December 1, 2009 DATA OUT 2 ...
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... Driving the CS# chip select input pin to the logic low state again will automatically send the device out of the standby mode and into the active mode. Figure 11.4 Read Identification Command Sequence and Data Out Sequence CS# SCK SI SO December 1, 2009 S25FL128R_00_02 ( ...
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... Device Identification Byte 0 Byte 1 01h 20h 01h 20h S25FL128R Manufacturer/Device Identification Byte Byte Byte Byte Byte Extended Device Identification Byte 2 Byte 3 18h 03h 18h 03h S25FL128R_00_02 December 1, 2009 Byte 4 00h 01h ...
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... CS# 0 SCK SCK December 1, 2009 S25FL128R_00_02 ( Figure 11.6 Serial READ_ID Instruction Sequence ...
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... S25FL128R ADD ( Manufacture ID Device ID Address Data 00000h 01h 00001h 17h S25FL128R_00_02 December 1, 2009 Byte Byte 1 2 ...
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... The host system should check the Write In Progress (WIP) bit before sending a new command to the device if an operation is already in progress. sequence, which also shows that it is possible to read the Status Register continuously until CS# is driven high. December 1, 2009 S25FL128R_00_02 ( Figure 11 ...
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... Mode 3 SCK Mode Table 11.3 S25FL128R Status Register (Uniform 256 KB sector) Bit Function 1 = Protects when WP#/ACC is low Status Register Write Disable protection, even when WP#/ACC is low — — — Not used Block Protect 000– ...
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... Protect (WP#/ACC) signal. When SRWD is set to 1 and WP#/ACC is driven low, the device enters the Hardware Protected mode. The non-volatile bits of the Status Register (SRWD, BP bits) become read-only bits and the device ignores any Write Status Register (WRSR) command. December 1, 2009 S25FL128R_00_02 ( ...
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... Once in the parallel mode, the flash memory will not exit the parallel mode until a Parallel Mode Exit (45h) command is given to the flash device, or upon power-down or power-up sequence Table 11.3, S25FL128R Status Register (Uniform 256 KB sector) on page 28 Figure 11.12 Write Status Register (WRSR) Command Sequence CS ...
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... Write Enable Latch to 0 before the operation completes (the exact timing is not specified). The device does not execute a Page Program (PP) command that specifies a page that is protected by the Block Protect bits (see December 1, 2009 S25FL128R_00_02 ( Table 11 ...
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... Data Byte MSB S25FL128R Data Byte MSB Data Byte 256 MSB S25FL128R_00_02 December 1, 2009 ...
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... Programming in parallel mode requires an “Parallel mode Entry” command (55h) before the program command. Once in the parallel mode, the flash memory will not exit parallel mode until an “Exit Parallel Mode” (45h) command is given to the flash device, or upon power down / power up sequence completion. December 1, 2009 S25FL128R_00_02 ( Figure 11 ...
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... SE command. CS# must be 13). Figure 11.16 Sector Erase (SE) Command Sequence Command 23 22 MSB S25FL128R Figure 11.16 . The Status Register may 24-bit Address S25FL128R_00_02 December 1, 2009 and ...
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... Write Enable Latch to 0 before the operation completes (the exact timing is not specified). The device only executes a BE command if all Block Protect bits (BP2:BP0 or BP3:BP0) are 0 (see on page 13). Otherwise, the device ignores the command. SO/PO[7-0] December 1, 2009 S25FL128R_00_02 ( Figure 11.17 Bulk Erase (BE) Command Sequence CS# ...
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... Table 17.1 on page 42). DP 11.13 and 11.14). Figure 11.18 Deep Power Down (DP) Command Sequence Command Standby Mode S25FL128R Figure 11.18 and Table 11.6. the device enters the DP mode and current DP Deep Power-down Mode S25FL128R_00_02 December 1, 2009 ...
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... Driving the CS# chip select input pin to the logic low state again will automatically send the device out of the standby mode and into the active mode. December 1, 2009 S25FL128R_00_02 ( after the 8-bit RES command byte ...
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... Dummy Bytes MSB Byte Electronic ID 1 Deep Power-down Mode S25FL128R RES Electronic ID out Standby Mode t RES Standby Mode S25FL128R_00_02 December 1, 2009 ...
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... V HH ACC Voltage Rise and Fall Time t VHH ACC command December 1, 2009 S25FL128R_00_02 ( Table 11.6 Command Definitions Description Command Code Read Data Bytes 03h (0000 0011) Read Data Bytes at Higher Speed ...
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... Figure 13.2 Power-down and Voltage Drop Vcc (max Device Access Allowed V (min) CC (cut-off) V (low S25FL128R reaches the allowable values as follows CC rises to the threshold at power-down, all CC Full Device Access Time Device Access t PU Allowed Time S25FL128R_00_02 December 1, 2009 CC feed. ...
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... Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. December 1, 2009 S25FL128R_00_02 ( Table 13 ...
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... Rating –40°C to +85°C 2.7V to 3.6 V Table 18.1 Min Typ. Max 2.7 3 200 3 10 max 2 max 2 –0 0.4 V – 0.6 CC S25FL128R_00_02 December 1, 2009 Unit µA µA µA µ ...
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... 18. Test Conditions 0.8 V Input Levels 0.2 V Symbol C L December 1, 2009 S25FL128R_00_02 ( Figure 18.1 AC Measurements I/O Waveform CC CC Table 18.1 Test Specifications Parameter Load Capacitance Input Rise and Fall Times Input Pulse Voltage ...
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... S25FL128R_00_02 December 1, 2009 Unit MHz MHz V/ns V/ µs µs ...
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... Symbol C_IN C_OUT CS# t CSH SCK SI Hi-Z SO CS# SCK December 1, 2009 S25FL128R_00_02 ( Table 19.2 Capacitance Parameter Input Capacitance (applies to SCK, PO7-PO0, SI, CS#) Output Capacitance (applies to PO7-PO0, SO) Figure 19.1 SPI Mode 0 (0,0) Input Timing t CSS ...
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... Figure 19.4 Write Protect Setup and Hold Timing during WRSR when SRWD=1 WP#/ACC CS# SCK Figure 19.3 HOLD# Timing WPS Hi-Z S25FL128R WPH S25FL128R_00_02 December 1, 2009 ...
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... L2 .010 BSC N 8 θ 0˚ θ1 5˚ θ2 0˚ December 1, 2009 S25FL128R_00_02 ( NOTES: 1. ALL DIMENSIONS ARE IN BOTH INCHES AND MILLMETERS. SOC 008 (mm) 2. DIMENSIONING AND TOLERANCING PER ASME Y14.5M - 1994. 3. DIMENSION D DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS ...
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... THIS CHAMFER FEATURE IS OPTIONAL NOT PRESENT, 8˚ THEN A PIN 1 IDENTIFIER MUST BE LOCATED WITHIN THE INDEX AREA INDICATED. 15˚ 10. LEAD COPLANARITY SHALL BE WITHIN 0. MEASURED 0˚ FROM THE SEATING PLANE. S25FL128R 3601 \ 16-038.03 \ 8.31.6 S25FL128R_00_02 December 1, 2009 ...
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... D 6.00 BSC E 8.00 BSC A 0.70 0.75 0.80 A1 0.00 0.02 0.05 L1 0.15 MAX. θ 0 --- 12 K 0.20 MIN. December 1, 2009 S25FL128R_00_02 ( (DATUM PIN #1 ID R0. SIDE VIEW DATUM A L1 10. TERMINAL TIP e 4. DETAIL "A" NOTES: 1. DIMENSIONING AND TOLERANCING CONFORMS TO ASME Y14.5M-1994. ...
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... Revision History Section Revision 01 (October 19, 2009) Initial release. Revision 02 (December 1, 2009) Global Removed all references to P/E Error Status Register Bit Description S25FL128R S25FL128R_00_02 December 1, 2009 ...
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... Spansion LLC in the United States and other countries. Other names used are for informational purposes only and may be trademarks of their respective owners. December 1, 2009 S25FL128R_00_02 ( ® ...