HD49334AHNP Renesas Electronics Corporation., HD49334AHNP Datasheet - Page 14

• Manufacturer Part Number: HD49334AHNP
• Description: Cds/pga & 10-bit A/d Converter
• Manufacturer: Renesas Electronics Corporation.

HD49334ANP/AHNP
Serial Interface Specifications
Rev.2.00 May 20, 2005 page 12 of 21
Table 10 Serial Data Function List
Notes: 1.
DI 00 (LSB)
DI 01
DI 02
DI 03
DI 04
DI 05
DI 06
DI 07
DI 08
DI 09
DI 10
DI 11
DI 12
DI 13
DI 14
DI 15 (MSB)
2.
3.
4.
5.
6.
7.
8.
2 byte continuous communications.
SDATA is latched at SCK rising edge.
Insert 16 clocks of SCK while CS is low.
Data is invalid if data transmission is aborted during transmission.
The gain conversion table differs in the CDSIN input mode and the ADCIN input mode.
STBY: Reference voltage generator circuit is in the operating state.
SLP: All circuits are in the sleep state.
This bit is used for the IC testing, and cannot be used by the user.
The use of this address is prohibited.
Circuit current and the frequency characteristic are switched.
Data = 0: 36 MHz guarantee
Data = 1: 25 MHz guarantee
PGA gain setting (LSB)
PGA gain setting
PGA gain setting
PGA gain setting
PGA gain setting
PGA gain setting
PGA gain setting
PGA gain setting (MSB)
CSEL
Cannot be used.
All low
Cannot be used.
All low
Low: CDSIN input mode
High: CIN input mode
Resister 0
CS
SCK
SDATA
Low
Low
Low
t
INT
t
Latches SDATA
at SCK rising edge
su
1
DI
00
SLP
STBY
Output mode setting (LINV)
Output mode setting (MINV)
Output mode setting (TEST0)
SHA-fsel [0] (LSB)
SHA-fsel [1] (MSB)
SHSW-fsel [0] (LSB)
SHSW-fsel [1]
SHSW-fsel [2]
SHSW-fsel [3] (MSB)
Figure 7 Serial Interface Timing Specifications
DI
t
01
ho
Cannot be used.
All low
Low: Normal operation mode
High: Sleep mode
Low: Normal operation mode
High: Standby mode
Resister 1
DI
02
High
Low
Low
DI
03
SHAMP
frequency
character-
istics
switching
SHSW
frequency
character-
istics
switching
f
DI
SCK
04
DI
05
Clamp-level [0] (LSB)
Clamp-level [1]
Clamp-level [2]
Clamp-level [3]
Clamp-level [4] (MSB)
HGstop-Hsel [0]
HGstop-Hsel [1]
HGain-Nsel [0]
HGain-Nsel [1]
Low_PWR
SPinv,
SPSIG/SPBLK/PBLK inversion
OBPinv, OBP inversion
RESET
DI
06
Low: Reset mode
High: Normal operation mode
DI
Resister 2
07
High
Low
Low
DI
08
High-speed
lead-in
gain
multiplication
High-speed
lead-in
cancellation
time
DI
09
DI
10
C-Bias off
Output mode setting (TEST1)
DI
11
0
0
0
0
0
1
0
0
1
Cannot be used.
All low
DI
12
Data is determined
at CS rising edge
Resister 3
Cannot be used.
High
High
DI
Low
13
DI
14
f
t
t
t
SCK
INT
su
ho
DI
1, 2
15
Timing Specifications
t
INT
2
Test Mode (can not be used)
Resister 4 to 7 *
Cannot be used.
50 ns
50 ns
50 ns
Min
Low to High
Low to High
High
5 MHz
Max
7