HD49334AHNP Renesas Electronics Corporation., HD49334AHNP Datasheet - Page 19

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HD49334AHNP

Manufacturer Part Number
HD49334AHNP
Description
Cds/pga & 10-bit A/d Converter
Manufacturer
Renesas Electronics Corporation.
Datasheet

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HD49334ANP/AHNP
Electrical Characteristics (cont.)
• Items for CDSIN Input Mode
Item
Consumption current (1)
Consumption current (2)
CCD offset tolerance range
Timing specifications (1)
Timing specifications (2)
Timing specifications (3)
Timing specifications (4)
Timing specifications (5)
Timing specifications (6)
Timing specifications (7)
Timing specifications (8)
Timing specifications (9)
Timing specifications (10)
Clamp level
PGA gain at CDS input
Note : Values within parentheses ( ) are for reference.
• Items for ADCIN Input Mode
Item
Consumption current (3)
Consumption current (4)
Timing specifications (11)
Timing specifications (12)
Timing specifications (13)
Timing specifications (14)
Timing specifications (15)
Input current at ADC input
Clamp level at ADC input
PGA gain at ADC input
Note : Values within parentheses ( ) are for reference.
Rev.2.00 May 20, 2005 page 17 of 21
Symbol
I
I
V
t
t
t
t
t
t
t
t
t
t
CLP(00)
CLP(09)
CLP(31)
PGA(0)
PGA(63)
PGA(127)
PGA(191)
PGA(255)
Symbol
I
I
t
t
t
t
t
IIN
OF2
GSL(0)
GSL(63)
GSL(127)
GSL(191)
GSL(255)
DD1
DD2
CDS1
CDS2
CDS3
CDS4
CDS5
CDS6
CDS7
CDS8
CHLD9
COD10
DD3
DD4
ADC1
ADC2
ADC3
AHLD4
AOD5
CCD
CIN
(Unless othewide specified, Ta = 25°C, AV
Min
(–100)
Typ × 0.8
Typ × 0.8
Typ × 0.85
1
11
11
3
–4.4
4.1
12.5
21.0
29.4
Min
Typ × 0.85
Typ × 0.85
10
–110
0.45
1.36
2.27
3.18
4.08
Typ
45.0
23.5
(1.5)
1/4f
(1.5)
1/4f
1/2f
5
7
16
(14)
(32)
(76)
–2.4
6.1
14.5
23.0
31.4
Typ
30.0
17.0
(6)
1/2f
1/2f
14.5
23.5
(512)
0.57
1.71
2.86
4.00
5.14
CLK
CLK
CLK
ADCLK
ADCLK
Max
38.0
21.5
Typ × 1.15
Typ × 1.15
31.5
110
0.72
2.16
3.60
5.04
6.47
Max
54.5
31.0
(100)
Typ × 1.2
Typ × 1.2
Typ × 1.15
9
24
–0.4
8.1
16.5
25.0
33.4
DD
Unit
mA
mA
ns
ns
ns
ns
ns
µA
LSB
Times
Times
Times
Times
Times
Unit
mA
mA
mV
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LSB
LSB
LSB
dB
dB
dB
dB
dB
= 3.0 V, DV
Test Conditions
f
f
C
V
CLK
CLK
IN
L
Test Conditions
f
f
C
CLK
CLK
= 10 pF
L
= 1.0 V to 2.0 V
= 36 MHz
= 25 MHz
= 10 pF
= 36 MHz
= 25 MHz
DD
= 3.0 V, and R
Remarks
CDSIN mode
LoPwr = low
CDSIN mode
LoPwr = high
See table 8
Remarks
ADCIN mode
LoPwr = low
ADCIN mode
LoPwr = high
See table 9
BIAS
= 33 kΩ)

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