HD49340F Renesas Electronics Corporation., HD49340F Datasheet
HD49340F
Related parts for HD49340F
HD49340F Summary of contents
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... HD49340F/HF CDS/PGA & 10-bit A/D Converter Description The HD49340F/ CMOS IC that provides CDS-PGA analog processing (CDS/PGA) suitable for CCD camera digital signal processing systems together with a 10-bit A/D converter in a single chip. Functions • Correlated double sampling • PGA • Offset compensation • ...
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... HD49340F/HF Pin Arrangement VRM VRT VRB OEB SDATA SCK Pin Description Pin No. Symbol Description connection pin Digital output connection pin 13 DRDV Output buffer power supply ( Digital ground ( Digital ground (0 V) ...
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... HD49340F/HF Pin Description (cont.) Pin No. Symbol Description 32 BIAS Internal bias pin Connect a 33 kΩ resistor between BIAS and Analog power supply ( connection pin 35 AV Analog ground ( ADCIN ADC input pin 37 VRM Reference voltage pin 1 Connect a 0.1 µF ceramic capacitor between VRM and AV ...
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... HD49340F/HF Input/Output Equivalent Circuit Pin Name Digital output Digital input ADCLK, OBP, SPBLK, SPSIG, CS, SCK, SDATA, PBLK, OEB Analog CDSIN ADCIN BLKSH, BLKFB, BLKC VRT, VRM, VRB BIAS Rev.1.0, Apr 20, 2004, page Equivalent Circuit DIN STBY DV DD Digital input Note: Only OEB is pulled down to about 70 k ...
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... HD49340F/HF Block Diagram ADCIN 27 PBLK 26 CDSIN 26 CDS BLKSH 28 BLKC 28 DC offset BLKFB 29 compensation circuit 17 Rev.1.0, Apr 20, 2004, page Timing generator 10-bit PGA ADC Serial Bias interface generator OEB ...
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... VRT BLKFB C3 Figure 1 HD49340F/HF Functional Block Diagram 1. CDS (Correlated Double Sampling) Circuit The CDS circuit extracts the voltage differential between the black level and a signal including the black level. The black level is directly sampled using the SPBLK pulse, buffered by the SHAMP, then provided to the CDSAMP ...
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... HD49340F/HF 2. PGA Circuit The PGAMP is the programmable gain amplifier for the latter stage. The PGAMP and the CDSAMP set the gain using 8 bits of register. The equation below shows how the gain changes when register value N is from 0 to 255. In CDSIN mode: Gain = (–2. 0.132 dB) × N (LOG linear). ...
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... HD49340F/HF 6. ADC Digital Output Control Function The ADC digital output includes the functions output enable, code conversion, and test mode. Tables 3, 4 and 5 show the output functions and the codes. Table 3 ADC Digital Output Functions Hi ...
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... HD49340F/HF 7. Adjustment of Black-Level S/H Response Frequency Characteristics The CR time constant that is used for sampling/hold (S/H) at the black level can be adjusted by changing the register settings, as shown in table 6. Table 6 SHSW CR Time Constant Setting SHSW-fsel (Register setting) [0] [1] [ Time Constant (Typ) 2.20 nsec (cutoff frequency conversion) ...
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... HD49340F/HF Timing Chart Figure 2 shows the timing chart when CDSIN and ADCIN input modes are used When CDSIN input mode is used N CDSIN SPBLK SPSIG ADCLK When ADCIN input mode is used N+1 N ADCIN ADCLK Note: The phases of SPBLK and SPSIG are those when the serial data SPinv bit is set to low. ...
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... HD49340F/HF Detailed Timing Specifications Detailed Timing Specifications when CDSIN Input Mode is Used Figure 3 shows the detailed timing specifications when the CDSIN input mode is used, and table 8 shows each timing specification. CDSIN SPBLK SPSIG ADCLK Note: 1. When serial data Spinv bit is set to low. (When the Spinv bit is set to high, the polarities of the SPBLK and the SPSIG are inverted ...
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... HD49340F/HF Detailed Timing Specifications at Pre-Blanking Figure 5 shows the pre-blanking detailed timing specifications. PBLK Digital output (D0 to D9) When serial data SPinv bit is set to low (When the SPinv is set to high, the PBLK polarity is inverted.) Figure 5 Detailed Timing Specifications at Pre-Blanking Detailed Timing Specifications when ADCIN Input Mode is Used Figure 6 shows the detailed timing chart when ADCIN input mode is used, and table 9 shows each timing specification ...
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... HD49340F/HF Serial Interface Specifications Table 10 Serial Data Function List Resister (LSB) Low DI 01 Low DI 02 Low DI 03 SLP Cannot be used. All low DI 04 STBY DI 05 PGA gain setting (LSB) Output mode setting (LINV PGA gain setting Output mode setting (MINV) ...
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... HD49340F/HF Explanation of Serial Data of CDS Part Serial data of CDS part has the following functions. • PGA gain (D5 to D12 of register 0) Details are referred to page 6 block diagram. At CDS_in mode: –2. 0.132 dB × N (Log linear) At ADC_in mode: 0.57 times + 0.01784 times × N (Times linear) ∗ ...
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... HD49340F/HF • Clamp ( register 2) Determine the OB part level with digital code of ADC output. Clamp level = setting data × Default data LSB. • HGstop-Hsel, HGain-Nsel (D8 to D11 of register 2) Determine the lead-in speed of OB clamp. Details are referred to page 7. PGA gain need to be changed for switch the high speed leading mode. Transfer the gain +1/– ...
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... HD49340F/HF Ripple (pseudo outline made by quantized error) occurres on the point which swithing the ADC output multiple bit in parallel. When switching the several of ADC output at the same time, ripple (pseudo outline caused by miss quantization) occurs to the image. Differential code and gray code are recommended for this countermeasure. ...
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... Item Power supply voltage Analog input voltage Digital input voltage Operating temperature Power dissipation Storage temperature Power supply voltage range (HD49340HF) Power supply voltage range (HD49340F) Notes indicates AV and and DV must be commonly connected outside the IC. When they are separated by a noise filter, the ...
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... HD49340F/HF Electrical Characteristics (cont.) • Items for CDSIN Input Mode Item Symbol Consumption current (1) I DD1 Consumption current (2) I DD2 CCD offset tolerance range V CCD Timing specifications (1) t CDS1 Timing specifications (2) t CDS2 Timing specifications (3) t CDS3 Timing specifications (4) t CDS4 ...
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... Start control SPSIG of TG and ADCLK camera DSP etc. OBP HD49340F/HF serial data transfer RESET bit Automatic offset calibration The following describes the above serial data transfer. For details on registers 0, 1, and 2, refer to table 10. (1) Register 2 setting : Set all bits in register 2 to the usage condition, and set the RESET bit to low. ...
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... At power-on, automatic adjustment of the offset voltage generated from PGA, ADC, etc., must be implemented in accordance with the power-on operating sequence (see page 19). Rev.1.0, Apr 20, 2004, page should be made off-chip Digital Noise filter +3. HD49340F/ and and DV are isolated by a noise filter, DD Example of noise filter 100 H 0 ...
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... C18 C19 C21 C22 0.1 0.1 0.1 0.1 0.1 C12 C11 0.1 0 BLKSH 28 BLKFB 29 CDSIN 30 HD49340F/HF (CDS/PGA+ADC) BLKC 31 BIAS ADCIN C16 47/6 C17 C18 C19 C21 C22 0.1 0.1 0.1 0.1 0.1 ...
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... HD49340F/HF Package Dimensions 9.0 ± 0 *0.21 ± 0.05 0.19 ± 0.04 *Dimension including the plating thickness Base material dimension Rev.1.0, Apr 20, 2004, page 7 0.08 M 0.75 0.75 0.50 ± 0.10 0.10 Package Code JEDEC JEITA Mass (reference value January, 2003 Unit: mm 1.00 0˚ – 8˚ FP-48C — ...
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Sales Strategic Planning Div. Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble ...