HD49340F Renesas Electronics Corporation., HD49340F Datasheet - Page 13

• Manufacturer Part Number: HD49340F
• Description: Cds/pga & 10-bit A/d Converter
• Manufacturer: Renesas Electronics Corporation.

HD49340F/HF
Serial Interface Specifications
Rev.1.0, Apr 20, 2004, page 13 of 22
Table 10 Serial Data Function List
Notes: 1.
DI 00 (LSB)
DI 01
DI 02
DI 03
DI 04
DI 05
DI 06
DI 07
DI 08
DI 09
DI 10
DI 11
DI 12
DI 13
DI 14
DI 15 (MSB)
CS
SCK
SDATA
2.
3.
4.
5.
6.
7.
8.
2 byte continuous communications.
SDATA is latched at SCK rising edge.
Insert 16 clocks of SCK while CS is low.
Data is invalid if data transmission is aborted during transmission.
The gain conversion table differs in the CDSIN input mode and the ADCIN input mode.
STBY: Reference voltage generator circuit is in the operating state.
SLP: All circuits are in the sleep state.
This bit is used for the IC testing, and cannot be used by the user.
The use of this address is prohibited.
Circuit current and the frequency characteristic are switched.
Data = 0: 36 MHz guarantee
Data = 1: 25 MHz guarantee
PGA gain setting (LSB)
PGA gain setting
PGA gain setting
PGA gain setting
PGA gain setting
PGA gain setting
PGA gain setting
PGA gain setting (MSB)
CSEL
t
Low: CDSIN input mode
High: ADCIN input mode
INT
Latches SDATA
at SCK rising edge
t
Resister 0
su
Cannot
be used.
All low
Cannot
be used.
All low
1
Low
Low
Low
DI
00
DI
t
01
ho
DI
02
SLP
STBY
Output mode setting (LINV)
Output mode setting (MINV)
Output mode setting (TEST0)
SHA-fsel [0] (LSB)
SHA-fsel [1] (MSB)
SHSW-fsel [0] (LSB)
SHSW-fsel [1]
SHSW-fsel [2]
SHSW-fsel [3] (MSB)
Figure 8 Serial Interface Timing Specifications
Low: Normal operation mode
High: Sleep mode
Low: Normal operation mode
High: Standby mode
DI
03
Resister 1
Cannot
be used.
All low
High
Low
Low
f
DI
SCK
04
SHAMP
frequency
character-
istics
switching
SHSW
frequency
character-
istics
switching
DI
05
DI
06
Clamp-level [0] (LSB)
Clamp-level [1]
Clamp-level [2]
Clamp-level [3]
Clamp-level [4] (MSB)
HGstop-Hsel [0]
HGstop-Hsel [1]
HGain-Nsel [0]
HGain-Nsel [1]
Low_PWR
SPinv,
SPSIG/SPBLK/PBLK inversion
OBPinv, OBP inversion
RESET
DI
07
Low: Reset mode
High: Normal operation mode
Resister 2
DI
High
Low
Low
08
High-speed
lead-in
gain
multiplication
High-speed
lead-in
cancellation
time
DI
09
DI
10
C-Bias off
Gray code [0] (TEST1)
Gray code [1]
Ave_4H
Gray_test [0]
Gray_test [1]
Gray_test [2]
0
0
1
0
0
1
DI
11
Resister 3
DI
12
Data is determined
at CS rising edge
High
High
Low
Cannot
be used.
DI
13
f
t
t
t
SCK
INT
su
ho
1, 2
DI
Timing Specifications
14
Test Mode (can not be used)
DI
15
t
Cannot be used.
50 ns
50 ns
50 ns
Resister 4 to 7
INT
Min
Low to High
Low to High
2
High
5 MHz
Max