HD49340F Renesas Electronics Corporation., HD49340F Datasheet - Page 6

• Manufacturer Part Number: HD49340F
• Description: Cds/pga & 10-bit A/d Converter
• Manufacturer: Renesas Electronics Corporation.

HD49340F/HF
Internal Functions
Functional Description
• CDS input
• ADC input
• Automatic offset calibration of PGA and ADC
• DC offset compensation feedback for CCD and CDS
• Pre-blanking
• Digital output enable function
Notes: 1. It is not
Operating Description
Figure 1 shows CDS/PGA + ADC function block.
1. CDS (Correlated Double Sampling) Circuit
Rev.1.0, Apr 20, 2004, page 6 of 22
 CCD low-frequency noise is suppressed by CDS (correlated double sampling).
 The signal level is clamped at 14 LSB to 76 LSB by resister during the OB period. *
 Gain can be adjusted using 8 bits of register (0.132 dB steps) within the range from –2.36 dB to 31.40 dB. *
 The center level of the input signal is clamped at 512 LSB (Typ).
 Gain can be adjusted using 8 bits of register (0.01784 times steps) within the range from 0.57 times (–4.86 dB)
 CDS input operation is protected by separating it from the large input signal.
 Digital output is set at clamp level by resister.
The CDS circuit extracts the voltage differential between the black level and a signal including the black level. The
black level is directly sampled at C1 by using the SPBLK pulse, buffered by the SHAMP, then provided to the
CDSAMP.
The signal level is directly sampled at C2 by using the SPSIG pulse, and provided to CDSAMP (see figure 1). The
difference between these two signal levels is extracted by the CDSAMP, which also operates as a programmable
gain amplifier at the previous stage. The CDS input is biased with VRT (2 V) during the SPBLK pulse validation
period. During the PBLK period, the above sampling and bias operation are paused.
to 5.14 times (14.22 dB). *
2. Full-scale digital output is defined as 0 dB (one time) when 1 V is input.
CDSIN
covered by warranty when 14LSB settings
VRT
BLKFB
C1
C2
Figure 1 HD49340F/HF Functional Block Diagram
SH
AMP
1
C3
ADCIN
CDS
AMP
BLKSH
Gain setting
(register)
Current
DAC
C4
BLKC
PG
AMP
DAC
Clamp data
(register)
10-bit
ADC
calibration
DC offset
feedback
1
Offset
logic
logic
OBP
D0 to D9
2