HD49340HNP Renesas Electronics Corporation., HD49340HNP Datasheet
HD49340HNP
Related parts for HD49340HNP
HD49340HNP Summary of contents
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... ADC • Operates using only the 3 V voltage • Corresponds to switching mode of power dissipation and operating frequency Power dissipation: 120 mW (Typ), maximum frequency: 36 MHz (HD49340HNP) Power dissipation (Typ), maximum frequency: 25 MHz (HD49340NP) • ADC direct input mode • QFN 36-pin package Features • ...
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HD49340NP/HNP Pin Arrangement VRM VRT VRB SDATA SCK Pin Description Pin No. Symbol Description Digital output 10 DRDV Output buffer power supply ( Digital ground (0 V) ...
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HD49340NP/HNP Pin Description (cont.) Pin No. Symbol Description 31 DV Digital power supply ( Digital ground ( Serial interface control input pin 34 SDATA Serial data input pin 35 SCK Serial clock ...
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HD49340NP/HNP Block Diagram ADCIN 27 PBLK 26 CDSIN 26 CDS BLKSH 28 BLKC 28 DC offset BLKFB 29 compensation circuit 17 Rev.1.0 Apr 20, 2004 page Timing generator 10bit ...
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HD49340NP/HNP Internal Functions Functional Description • CDS input CCD low-frequency noise is suppressed by CDS (correlated double sampling). The signal level is clamped at 14 LSB to 76 LSB by resister during the OB period. * Gain ...
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HD49340NP/HNP 2. PGA Circuit The PGAMP is the programmable gain amplifier for the latter stage. The PGAMP and the CDSAMP set the gain using 8 bits of register. The equation below shows how the gain changes when register value N ...
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HD49340NP/HNP 6. ADC Digital Output Control Function The ADC digital output includes the functions output enable, code conversion, and test mode. Tables 3, 4 and 5 show the output functions and the codes. Table 3 ADC Digital Output Functions H ...
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HD49340NP/HNP 7. Adjustment of Black-Level S/H Response Frequency Characteristics The CR time constant that is used for sampling/hold (S/H) at the black level can be adjusted by changing the register settings, as shown in table 6. Table 6 SHSW CR ...
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HD49340NP/HNP Timing Chart Figure 2 shows the timing chart when CDSIN and ADCIN input modes are used When CDSIN input mode is used N CDSIN SPBLK SPSIG ADCLK When ADCIN input mode is ...
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HD49340NP/HNP Detailed Timing Specifications Detailed Timing Specifications when CDSIN Input Mode is Used Figure 3 shows the detailed timing specifications when the CDSIN input mode is used, and table 8 shows each timing specification. CDSIN SPBLK SPSIG ADCLK D0 to ...
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HD49340NP/HNP Detailed Timing Specifications at Pre-Blanking Figure 5 shows the pre-blanking detailed timing specifications. PBLK Digital output ADC (D0 to D9) data When serial data SPinv bit is set to low (When the SPinv is set to high, the PBLK ...
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HD49340NP/HNP Serial Interface Specifications Table 10 Serial Data Function List Resister (LSB) Low DI 01 Low DI 02 Low Low: Normal operation mode DI 03 SLP High: Sleep mode Cannot be used. All low Low: Normal operation ...
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HD49340NP/HNP Explanation of Serial Data of CDS Part Serial data of CDS part has the following functions. • PGA gain (D5 to D12 of register 0) Details are referred to page 5 block diagram. At CDS_in mode: –2. ...
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HD49340NP/HNP • Clamp ( register 2) Determine the OB part level with digital code of ADC output. Clamp level = setting data × Default data LSB. • HGstop-Hsel, HGain-Nsel (D8 ...
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HD49340NP/HNP Ripple (pseudo outline made by quantized error) occurres on the point which swithing the ADC output multiple bit in parallel. When switching the several of ADC output at the same time, ripple (pseudo outline caused by miss quantization) occurs ...
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... HD49340NP/HNP Absolute Maximum Ratings Item Power supply voltage Analog input voltage Digital input voltage Operating temperature Power dissipation Storage temperature Power supply voltage range (HD49340HNP) Power supply voltage range (HD49340NP) Notes indicates AV and and DV must be commonly connected outside the IC. When they are separated by a noise filter, the ...
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HD49340NP/HNP Electrical Characteristics (cont.) • Items for CDSIN Input Mode Item Symbol Consumption current (1) I DD1 Consumption current (2) I DD2 CCD offset tolerance range V CCD Timing specifications (1) t CDS1 Timing specifications (2) t CDS2 Timing specifications ...
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HD49340NP/HNP Operation Sequence at Power SPBLK Start control SPSIG of TG and ADCLK camera DSP etc. OBP HD49340NP/HNP serial data transfer RESET bit Automatic offset calibration The following describes the above serial data transfer. For details on ...
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HD49340NP/HNP Notice for Use 1. Careful handling is necessary to prevent damage due to static electricity. 2. This product has been developed for consumer applications, and should not be used in non-consumer applications this IC is sensitive to ...
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HD49340NP/HNP Example of Recommended External Circuit At CDS Input from CCD out C14 0 C3 C4* R15 33 k C15 0 3.0 V Notes: 1. For C4, see table 5. 2. For C3, see ...
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HD49340NP/HNP Package Dimensions 6.20 ± 0.10 6.00 ± 0. 0.50 0.50 0.05 Rev.1.0 Apr 20, 2004 page 0.22 ± 0.05 1.00 Package Code JEDEC JEITA ...
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Sales Strategic Planning Div. Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble ...