HD49340HNP Renesas Electronics Corporation., HD49340HNP Datasheet - Page 7

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HD49340HNP

Manufacturer Part Number
HD49340HNP
Description
Cds/pga & 10-bit A/d Converter
Manufacturer
Renesas Electronics Corporation.
Datasheet
HD49340NP/HNP
6. ADC Digital Output Control Function
Table 3
Table 4
Table 5
Rev.1.0 Apr 20, 2004 page 7 of 21
Notes: 1. STBY, TEST, LINV, and MINV are set by register.
Output Pin
Output
codes
Output Pin
Output
codes
H
L
The ADC digital output includes the functions output enable, code conversion, and test mode. Tables 3, 4 and 5
show the output functions and the codes.
H
2. Mode setting for the PBLK is done by external input pins.
3. The polarity of the PBLK pin when the register setting is SPinv is low.
X
L
Steps
Steps
H
X
L
X
ADC Digital Output Functions
ADC Output Code
ADC Output Code (TEST1)
H
H
H
H
H
H
1020
1021
1022
1023
1020
1021
1022
1023
X
X
X
L
L
L
L
L
L
511
512
511
512
3
4
5
6
3
4
5
6
X
H
H
X
H
H
X
H
H
L
L
L
L
L
L
X
H
H
H
H
H
H
H
H
X
X
X
X
L
L
Hi-Z
Same as in table 4.
D9 is inverted in table 4.
D8 to D0 are inverted in table 4.
D9 to D0 are inverted in table 4.
Output code is set up to Clamp Level.
Same as in table 5.
D9 is inverted in table 5.
D8 to D0 are inverted in table 5.
D9 to D0 are inverted in table 5.
Output code is set up to Clamp Level.
D9
D9
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
D9
H
H
L
L
D8
H
H
D8
D8
L
L
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
D7
ADC Digital Output
H
H
L
L
D7
D7
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
D6
H
H
L
L
D5
H
H
D6
D6
L
L
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
D4
H
H
L
L
D5
D5
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
D3
H
H
L
L
D2
H
H
L
L
D4
D4
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
D1
H
H
L
L
D3
D3
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
D0
H
H
L
L
Low-power wait state
Normal operation
Pre-blanking
Normal operation
Pre-blanking
Test mode
D2
D2
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
Operating Mode
D1
D1
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
D0
D0
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L

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