HD49340HNP Renesas Electronics Corporation., HD49340HNP Datasheet - Page 11

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HD49340HNP

Manufacturer Part Number
HD49340HNP
Description
Cds/pga & 10-bit A/d Converter
Manufacturer
Renesas Electronics Corporation.
Datasheet
HD49340NP/HNP
Detailed Timing Specifications at Pre-Blanking
Figure 5 shows the pre-blanking detailed timing specifications.
Detailed Timing Specifications when ADCIN Input Mode is Used
Figure 6 shows the detailed timing chart when ADCIN input mode is used, and table 9 shows each timing specification.
Table 9
No.
(1)
(2), (3)
(4)
(5)
Rev.1.0 Apr 20, 2004 page 11 of 21
Timing
Signal fetch time
ADCLK t
ADCLK rising to digital output hold time
ADCLK rising to digital output delay time
Timing Specifications when ADCIN Input Mode is Used
WH
Digital output
(D0 to D9)
min./t
ADCIN
ADCLK
D0 to D9
PBLK
Figure 6 Detailed Timing Chart when ADCIN Input Mode is Used
WL
Figure 5 Detailed Timing Specifications at Pre-Blanking
min.
When serial data SPinv bit is set to low
(When the SPinv is set to high, the PBLK polarity is inverted.)
ADC
data
ADCLK
(2)
t
PBLK
2 clocks
Clamp level
(3)
Symbol
t
t
t
t
ADC1
ADC2, 3
AHLD4
AOD5
(1)
ADCLK
(shifts one clock cycle depending
on the PBLK input timing)
(4)
(5)
Min
Typ × 0.85
10
10 clocks
ADC
data
Typ
(6)
1/2f
14.5
23.5
Vth
V
ADCLK
DD
/2
V
V
Vth
OH
OL
Max
Typ × 1.15
31.5
Unit
ns
ns
ns
ns

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