HD49330AF Renesas Electronics Corporation., HD49330AF Datasheet - Page 12

• Manufacturer Part Number: HD49330AF
• Description: Cds/pga & 12-bit A/d Converter
• Manufacturer: Renesas Electronics Corporation.

HD49330AF/AHF
Detailed Timing Specifications at Pre-Blanking
Figure 5 shows the pre-blanking detailed timing specifications.
Detailed Timing Specifications when ADCIN Input Mode is Used
Figure 6 shows the detailed timing chart when ADCIN input mode is used, and table 9 shows each timing specification.
Table 9
No.
(1)
(2), (3)
(4)
(5)
Detailed Timing Specifications for Digital Output-Enable Control
Figure 7 shows the detailed timing specifications for digital output enable control. When the OEB pin is set to high,
output disable mode is entered, and the output state becomes High-Z.
Rev.1.0, Apr.05.2004, page 12 of 19
Timing
Signal fetch time
ADCLK t
ADCLK rising to digital output hold time
ADCLK rising to digital output delay time
Digital output
(D0 to D11)
Timing Specifications when ADCIN Input Mode is Used
OEB
WH
Figure 7 Detailed Timing Specifications for Digital Output Enable Control
min./t
Vth
Digital output
(D0 to D11)
Figure 6 Detailed Timing Chart when ADCIN Input Mode is Used
ADCIN
ADCLK
D0 to D11
PBLK
WL
Figure 5 Detailed Timing Specifications at Pre-Blanking
min.
t
t
HZ
LZ
When serial data SPinv bit is set to low
(When the SPinv is set to high, the PBLK polarity is inverted.)
ADC
data
ADCLK
(2)
t
PBLK
2 clocks
Clamp level
t
t
ZH
ZL
(3)
Symbol
t
t
t
t
ADC1
ADC2, 3
AHLD4
AOD5
DV
DV
(1)
DD
DD
ADCLK
(shifts one clock cycle depending
on the PBLK input timing)
(4)
(5)
/2
/2
Min
—
Typ × 0.85
10
—
12 clocks
DV
V
V
DV
OL
OH
DD
SS
ADC
data
Typ
(6)
1/2f
14.5
23.5
Vth
V
measurement load
measurement load
DD
ADCLK
DV
/2
V
V
Vth
SS
OH
OL
t
t
HZ
DV
10 pF
LZ
DV
, t
, t
DD
SS
ZL
ZH
Max
—
Typ × 1.15
—
31.5
2 k
10 pF
DV
SS
2 k
Unit
ns
ns
ns
ns