HD49330AF Renesas Electronics Corporation., HD49330AF Datasheet - Page 13

• Manufacturer Part Number: HD49330AF
• Description: Cds/pga & 12-bit A/d Converter
• Manufacturer: Renesas Electronics Corporation.

HD49330AF/AHF
Serial Interface Specifications
Rev.1.0, Apr.05.2004, page 13 of 19
Table 10 Serial Data Function List
Notes: 1.
DI 00 (LSB)
DI 01
DI 02
DI 03
DI 04
DI 05
DI 06
DI 07
DI 08
DI 09
DI 10
DI 11
DI 12
DI 13
DI 14
DI 15 (MSB)
CS
SCK
SDATA
2.
3.
4.
5.
6.
7.
8.
2 byte continuous communications.
SDATA is latched at SCK rising edge.
Insert 16 clocks of SCK while CS is low.
Data is invalid if data transmission is aborted during transmission.
The gain conversion table differs in the CDSIN input mode and the ADCIN input mode.
STBY: Reference voltage generator circuit is in the operating state.
SLP: All circuits are in the sleep state.
This bit is used for the IC testing, and cannot be used by the user.
Please do not set up in addition to "ALL Low".
This bit is used for the IC testing, and cannot be used by the user.
It is set to the state on the right of a column when RESET bit is set to low. The register
3 should transmit by setup on the right of a column.
PGA gain setting (LSB) *
PGA gain setting *
PGA gain setting *
PGA gain setting *
PGA gain setting *
PGA gain setting *
PGA gain setting *
PGA gain setting *
PGA gain setting *
PGA gain setting (MSB) *
YSEL
CSEL
Low: CDSIN input mode
High: YIN input mode
Low: CDSIN input mode
High: YIN input mode
t
INT
Resister 0
Latches SDATA
at SCK rising edge
t
su
1
Low
Low
Low
X
DI
00
5
5
5
5
5
5
5
5
DI
t
01
ho
5
5
DI
SLP
STBY
Output mode setting (LINV)
Output mode setting (MINV)
Output mode setting (TEST0)
SHA-fsel [0] (LSB)
SHA-fsel [1] (MSB)
SHSW-fsel [0] (LSB)
SHSW-fsel [1]
SHSW-fsel [2]
SHSW-fsel [3] (MSB)
02
Figure 8 Serial Interface Timing Specifications
Cannot be used. *
All low
Low: Normal operation mode
High: Sleep mode
Low: Normal operation mode
High: Standby mode
DI
03
Resister 1
High
Low
Low
f
DI
SCK
04
SHAMP
frequency
character-
istics
switching
SHSW
frequency
character-
istics
switching
DI
05
7
DI
06
Clamp-level [0] (LSB)
Clamp-level [1]
Clamp-level [2]
Clamp-level [3]
Clamp-level [4] (MSB)
HGstop-Hsel [0]
HGstop-Hsel [1]
HGain-Nsel [0]
HGain-Nsel [1]
LoPwr
SPinv,
SPSIG/SPBLK/PBLK inversion
OBPinv, OBP inversion
RESET
DI
07
Low: Normal mode
High: Low power mode
Low: Reset mode
High: Normal operation mode
Resister 2
High
Low
Low
DI
08
High-speed
lead-in
gain
multiplication
High-speed
lead-in
cancellation
time
DI
09
DI
10
YC-Bias off
Output mode setting (TEST1)
Average4, 4 lines average
Cannot be used. *
Cannot be used. *
Cannot be used. *
Cannot be used. *
Cannot be used. *
Cannot be used. *
DI
Cannot be used. *
All low
Cannot be used. *
All low
11
Resister 3
DI
12
High
High
Data is determined
at CS rising edge
Low
DI
13
f
t
t
t
SCK
INT
su
ho
8
8
8
8
8
8
1, 2
Low
Low
High
Low
Low
High
7
7
DI
Timing Specifications
14
Test Mode (can not be used)
DI
Cannot be used. *
All low
15
t
50 ns
50 ns
50 ns
Resister 4 to 7
INT
Min

Low to High
Low to High
2
High
5 MHz
Max



7