HD49330AF Renesas Electronics Corporation., HD49330AF Datasheet - Page 16

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HD49330AF

Manufacturer Part Number
HD49330AF
Description
Cds/pga & 12-bit A/d Converter
Manufacturer
Renesas Electronics Corporation.
Datasheet
HD49330AF/AHF
Operation Sequence at Power On
Rev.1.0, Apr.05.2004, page 16 of 19
V
Start control
of TG and
camera DSP
HD49330AF/AHF
serial data transfer
RESET bit
Automatic offset
calibration
The following describes the above serial data transfer. For details on registers 0, 1, 2, and 3, refer to table 10.
DD
(1) Register 2 setting
(2) Register 2 setting
(3) Register 0, 1 and 3 settings
SPBLK
SPSIG
ADCLK
OBP
etc.
or more
or more
0 ms
0 ms
: Set all bits in register 2 to the usage condition, and set the RESET bit to low.
: Cancel the RESET mode by setting the register 2 RESET bit to high.
: After the offset calibration is terminated, set registers 0, 1 and 3.
Do not change other register 2 settings. Offset calibration starts automatically.
Must be stable within the operating
power supply voltage range
(1) Register 2 setting
RESET = "Low"
2 ms or more
(RESET mode)
2 ms or more
(2) Register 2 setting
Offset calibration
(automatically starts
Ends after 40000 clock cycles
after RESET cancellation)
(RESET cancellation)
RESET = "High"
0 ms
or more
(3) Registers 0, 1
and 3 settings

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