LMX2487E National Semiconductor Corporation, LMX2487E Datasheet - Page 20

• Manufacturer Part Number: LMX2487E
• Description: 7.5 Ghz High Performance Delta-sigma Low Power Dual Pllatinum? Frequency Synthesizers With 3.0 Ghz Integer Pll
• Manufacturer: National Semiconductor Corporation

www.national.com
Functional Description
1.0 GENERAL
The LMX2487E consists of integrated N counters, R coun-
ters, and charge pumps. The TCXO, VCO and loop filter are
supplied external to the chip. The various blocks are de-
scribed below.
1.1 TCXO, OSCILLATOR BUFFER, AND R COUNTER
The oscillator buffer must be driven single-ended by a signal
source, such as a TCXO. The OSCout pin is included to pro-
vide a buffered output of this input signal and is active when
the OSC_OUT bit is set to one. The ENOSC pin can be also
pulled high to ensure that the OSCout pin is active, regardless
of the status of the registers in the LMX2487E.
The R counter divides this TCXO frequency down to the com-
parison frequency.
1.2 PHASE DETECTOR
The maximum phase detector operating frequency for the IF
PLL is straightforward, but it is a little more involved for the
RF PLL since it is fractional. The maximum phase detector
frequency for the LMX2487E RF PLL is 50 MHz. However,
this is not possible in all circumstances due to illegal divide
ratios of the N counter. The crystal reference frequency also
limits the phase detector frequency, although the doubler
helps with this limitation. There are trade-offs in choosing the
phase detector frequency. If this frequency is run higher, then
phase noise will be lower, but lock time may be increased due
to cycle slipping and the capacitors in the loop filter may be-
come rather large.
1.3 CHARGE PUMP
For the majority of the time, the charge pump output is high
impedance, and the only current through this pin is the Tri-
State leakage. However, it does put out fast correction pulses
that have a width that is proportional to the phase error pre-
sented at the phase detector.
The charge pump converts the phase error presented at the
phase detector into a correction current. The magnitude of
this current is theoretically constant, but the duty cycle is pro-
portional to the phase error. For the IF PLL, this current is not
programmable, but for the RF PLL it is programmable in 16
steps. Also, the RF PLL allows for a higher charge pump cur-
rent to be used when the PLL is locking in order to reduce the
lock time.
1.4 LOOP FILTER
The loop filter design can be rather involved. In addition to the
regular constraints and design parameters, delta-sigma PLLs
have the additional constraint that the order of the loop filter
should be one greater than the order of the delta sigma mod-
ulator. This rule of thumb comes from the requirement that the
loop filter must roll off the delta sigma noise at 20 dB/decade
faster than it rises. However, since the noise can not have
infinite power, it must eventually roll off. If the loop bandwidth
is narrow, this requirement may not be necessary. For the
purposes of discussion in this datasheet, the pole of the loop
filter at 0 Hz is not counted. So a second order filter has 3
components, a 3rd order loop filter has 5 components, and
the 4th order loop filter has 7 components. Although a 5th
order loop filter is theoretically necessary for use with a 4th
order modulator, typically a 4th order filter is used in this case.
The loop filter design, especially for higher orders can be
rather involved, but there are many simulation tools and ref-
(Note 8)
20
erences available, such as the one given at the end of the
functional description block.
1.5 N COUNTERS AND HIGH FREQUENCY INPUT PINS
The N counter divides the VCO frequency down to the com-
parison frequency. Because prescalers are used, there are
limitations on how small the N value can be. The N counters
are discussed in greater depth in the programming section.
Since the input pins to these counters ( FinRF and FinIF ) are
high frequency, layout considerations are important.
High Frequency Input Pins, FinRF and FinIF
It is generally recommended that the VCO output go through
a resistive pad and then through a DC blocking capacitor be-
fore it gets to these high frequency input pins. If the trace
length is sufficiently short ( < 1/10th of a wavelength ), then
the pad may not be necessary, but a series resistor of about
39 ohms is still recommended to isolate the PLL from the
VCO. The DC blocking capacitor should be chosen at least to
be 27 pF. It may turn out that the frequency is above the self-
resonant frequency of the capacitor, but since the input
impedance of the PLL tends to be capacitive, it actually is a
benefit to exceed the tune frequency. The pad and the DC
blocking capacitor should be placed as close to the PLL as
possible
Complementary High Frequency Pin, FinRF*
These inputs may be used to drive the PLL differentially, but
it is very common to drive the PLL in a single ended fashion.
A shunt capacitor should be placed at the FinRF* pin. The
value of this capacitor should be chosen such that the
impedance, including the ESR of the capacitor, is as close to
an AC short as possible at the operating frequency of the PLL.
100 pF is a typical value.
1.6 POWER PINS, POWER DOWN, AND POWER UP
MODES
It is recommended that all of the power pins be filtered with a
series 18 ohm resistor and then placing two capacitors shunt
to ground, thus creating a low pass filter. Although it makes
sense to use large capacitor values in theory, the ESR
( Equivalent Series Resistance ) is greater for larger capaci-
tors. For optimal filtering minimize the sum of the ESR and
theoretical impedance of the capacitor. It is therefore recom-
mended to provide two capacitors of very different sizes for
the best filtering. 1 µF and 100 pF are typical values. The
small capacitor should be placed as close as possible to the
pin.
The power down state of the LMX2487E is controlled by many
factors. The one factor that overrides all other factors is the
CE pin. If this pin is low, the part will be powered down. As-
serting a high logic level on this pin is necessary to power up
the chip, however, there are other bits in the programming
registers that can override this and put the PLL back in a
power down state. Provided that the voltage on the CE pin is
high, programming the RF_PD and IF_PD bits to zero guar-
antees that the part will be powered up. Programming either
one of these bits to one will power down the appropriate sec-
tion of the synthesizer, provided that the ATPU bit does not
override this.