LMX2485 National Semiconductor Corporation, LMX2485 Datasheet - Page 29

• Manufacturer Part Number: LMX2485
• Description: 50 Mhz - 3.0 Ghz High Performance Delta-sigma Low Power Dual Pllatinum 50 Mhz - 3.0 Ghz High Performance Delta-sigma Low Power Dual Pllatinum? Frequency Synthesizers With 800 Mhz Integer Pll
• Manufacturer: National Semiconductor Corporation

REGISTER
Programming Description
2.4 R3 REGISTER
2.4.1 IF_R[11:0] -- IF R Divider Value
For the IF R divider, the R value is determined by the IF_R[11:0] bits in the R3 register. The minimum value for IF_R is 3.
2.4.2 RF_CPG -- RF PLL Charge Pump Gain
This is used to control the magnitude of the RF PLL charge pump in steady state operation.
2.4.3 ACCESS -- Register Access word
It is mandatory that the first 5 registers R0-R4 be programmed. The programming of registers R5-R7 is optional. The
ACCESS[3:0] bits determine which additional registers need to be programmed. Any one of these registers can be individually
programmed. According to the table below, when the state of a register is in default mode, all the bits in that register are forced
to a default state and it is not necessary to program this register. When the register is programmable, it needs to be programmed
through the MICROWIRE. Using this register access technique, the programming required is reduced up to 37%.
The default conditions the registers is shown below:
Register
R3
R Value
R4
R5
R6
R7
4095
...
3
RF_CPG
10
12
13
14
15
11
0
1
2
3
4
5
6
7
8
9
ACCESS Bit
23
23
ACCESS[0]
ACCESS[1]
ACCESS[2]
ACCESS[3]
0
0
0
ACCESS[3:0]
22
22
0
0
0
0
1
.
21
21
0
0
0
20
20
0
0
0
0
1
.
Charge Pump State
19
19
0
0
0
RF_CPG[3:0]
18
18
0
1
0
0
0
.
10X
11X
12X
13X
14X
15X
16X
1X
2X
3X
4X
5X
6X
7X
8X
9X
17
17
0
0
0
(Continued)
0
1
.
16
16
0
0
0
Register Location
R4 Must be programmed manually.
Data[19:0]
15
DATA[19:0]
0
0
0
15
R3[20]
R3[21]
R3[22]
R3[23]
0
1
.
14
0
0
0
14
29
13
0
0
0
13
IF_R[11:0]
0
1
.
Typical RF Charge Pump Current at 3 Volts (µA)
12
0
0
0
12
11
0
0
1
11
IF_R[11:0]
0
1
.
10
0
0
0
10
9
0
0
0
0
1
.
9
8
0
0
1
8
1045
1140
1235
1330
1425
1520
7
0
0
0
190
285
380
475
570
665
760
855
950
95
7
Register Controlled
0
1
.
6
0
0
0
Must be set to 1
6
5
0
0
0
5
4
0
0
0
R5
R6
R7
0
1
.
4
C3
3
1
1
1
C3
3
0
C2
1
1
.
2
0
1
1
C2
2
1
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C1
1
1
0
1
C1
1
1
1
1
.
C0
0
1
1
1
C0
0
1