LMX2485 National Semiconductor Corporation, LMX2485 Datasheet - Page 32

• Manufacturer Part Number: LMX2485
• Description: 50 Mhz - 3.0 Ghz High Performance Delta-sigma Low Power Dual Pllatinum 50 Mhz - 3.0 Ghz High Performance Delta-sigma Low Power Dual Pllatinum? Frequency Synthesizers With 800 Mhz Integer Pll
• Manufacturer: National Semiconductor Corporation

www.national.com
Programming Description
2.5.6 OSC2X -- Oscillator Doubler Enable
When this bit is set to 0, the oscillator doubler is disabled and the TCXO frequency presented to the IF R and RF R counters is
equal to that of the input frequency of the OSCin pin. When this bit is set to 1, the TCXO frequency presented to the RF R counter
is doubled. Phase noise added by the doubler is negligible.
2.5.7 FM[1:0] -- Fractional Mode
Determines the order of the delta-sigma modulator. Higher order delta-sigma modulators reduce the spur levels closer to the
carrier by pushing this noise to higher frequency offsets from the carrier. In general, the order of the loop filter should be at least
one greater than the order of the delta-sigma modulator in order to allow for sufficient roll-off.
2.5.8 DITH[1:0] -- Dithering Control
Dithering is a technique used to spread out the spur energy. Enabling dithering can reduce the main fractional spurs, but can also
give rise to a family of smaller spurs. Whether dithering helps or hurts is application specific. Enabling the dithering may also
increase the phase noise. In most cases where the fractional numerator is zero, dithering usually degrades performance.
Dithering tends to be most beneficial in applications where there is insufficient filtering of the spurs. This often occurs when the
loop bandwidth is very wide or a higher order delta-sigma modulator is used. Dithering tends not to impact the main fractional
spurs much, but has a much larger impact on the sub-fractional spurs. If it is decided that dithering will be used, best results will
be obtained when the fractional denominator is at least 1000.
2.5.9 ATPU -- PLL Automatic Power Up
When this bit is set to 1, both the RF and IF PLL power up when the R0 register is written to. When the R0 register is written to,
the PD_RF and PD_IF bits are changed to 0 in the PLL registers. The exception to this case is when the CE pin is low. In this
case, the ATPU function is disabled.
OSC2X
0
1
FM
0
1
2
3
DITH
Frequency Presented to RF R Counter
0
1
2
3
2 x f
f
Disable the delta-sigma modulator. Recommended for test use only.
OSCin
(Continued)
OSCin
Fractional PLL mode with a 2nd order delta-sigma modulator
Fractional PLL mode with a 3rd order delta-sigma modulator
Fractional PLL mode with a 4th order delta-sigma modulator
32
Function
Dithering Mode Used
Frequency Presented to IF R Counter
Strong Dithering
Weak Dithering
Reserved
Disabled
f
OSCin